Getting Started

Arm SystemC Cycle Models simplify virtual prototype creation. Models that are IEEE std. 1666-2011-compliant allow you to rapidly assemble systems and integrate other Accellera SystemC and Transaction Level Modeling (TLM) component models to create accurate virtual prototypes.

Because models are the key to creating a virtual prototype, Arm supports a wide range of models in a variety of formats including:

  • Flexible SystemC model support for easy creation and integration

  • High performance cycle-accurate and implementation-accurate models compiled by Cycle Model Studio

  • Verilog and VHDL co-simulation with leading RTL Simulators

Platform Debug

Assembling system models is only part of the solution: the key lies in the ability to execute the prototype, examine the behavior of the system, and analyze key metrics. Arm Cycle Models provide debug interfaces tailored for both hardware and software engineers. You have full visibility and execution control of your design. Software engineers are able to view code, control the simulation at clock edge granularity, and examine registers and memories. Hardware engineers can examine signals, dump waveforms, and trace execution through the system. Run-time performance profiling gives you immediate feedback on system behavior during execution.

Architectural Analysis

Development and analysis of system architecture requires the accuracy to model key system characteristics, especially with complex bus architectures and multi-core communications models. Arm Cycle Models provide the accuracy, performance, and flexibility to model complex systems and perform the analysis required to make critical design decisions. Instead of ad-hoc model approximations and paper-and-pencil calculations, architects can now prove their design assumptions before committing to the design implementation. The unique benefits for architectural analysis enable first-turn success of your SoC:

  • Create cycle-accurate system models required for detailed architectural analysis and explore the performance impact of hardware/software trade-offs

  • Measure interconnect performance of complex bus architectures using actual system behavior to drive traffic

  • Quickly and easily make changes and explore design space alternatives before committing to an implementation

Hardware and Software System Validation

System validation requires the ability to model the entire system working together, and provide accurate models of both the hardware and software. Cycle-accurate virtual prototypes provide a way to develop and validate software before committing to physical hardware implementations. Effective driver and firmware development requires the detail and performance that is provided by Arm. The benefits for hardware/software system validation provide insight:

  • Speed system integration time by debugging your software on virtual platforms before physical prototypes are available

  • Reduce risk by validating hardware implementations using actual system software

  • Eliminate hardware physical prototype availability as a bottleneck to software development

  • Accelerate the process of debugging, implementing hardware or software changes, and then re-executing the system.

Accurate Models from Arm IP Exchange

Arm Cycle Model solutions leverage models from Arm IP Exchange. This web portal enables around the clock access to Arm IP. Models can be easily configured, built, downloaded, and managed, then integrated directly into a SystemC system. The benefits of Arm IP Exchange are numerous:

  • Configuration — IP Exchange understands the valid configuration options for each piece of Arm IP and only permits compatible combinations of these options to be chosen. 

  • Quality — Models are generated in a "clean" environment that is proven and continually regression tested. Arm IP Exchange understands the dependencies between the model and SystemC to ensure compatibility.

  • Usability — Models are configured using a short series of questions, which automatically adapt as answers are given, to ensure that only valid configurations are built. No RTL or design knowledge is required to configure or build a model.

  • Enhanced Satisfaction — Arm IP Exchange is available 24/7 allowing you to configure the model as and when you need it. You can easily check on the status of any model you requested to be automatically built.

  • IP Management — Arm IP Exchange maintains a secure history of user models and automatically issues a notification when a new revision or model is available. This secure history mechanism enables you to leverage IP and configurations that are used elsewhere within your organization.

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Answered Where should I ask my question? Latest 1 months ago by Oliver Beirne 1 replies 1137 views
Not answered Where do I find presentations and photos from SC'18? Started 1 years ago by John Linford 0 replies 5169 views
Suggested answer Disassembly differences Latest 15 hours ago by Broeker 2 replies 178 views
Answered STM32 UART DMA can receive first time correct then it receive nothing Latest 20 hours ago by Williams_W 4 replies 801 views
Suggested answer Hardcoded Breakpoint Preventing Program From Running Latest 22 hours ago by Cassandra 5 replies 2871 views
Suggested answer Where to start with ARM Trust-zone development for Cortex-A series? Latest yesterday by Westerville 3 replies 613 views
Suggested answer gnu GCC option to enforce 8-byte stack alignment (necessary for R52)? Latest yesterday by BenjaminEhlers 3 replies 367 views
Not answered compiling LLVM 11 Started yesterday by YHuerta 0 replies 118 views
Not answered ARM way how to handle and generate own run time error, like try raise catch Started yesterday by Silicium 0 replies 109 views
Suggested answer Problems about zero copy clImportMemoryARM Latest yesterday by m.x 2 replies 358 views
Answered Keil MDK5 HTTP server - form input names Latest yesterday by Murilo Machado 3 replies 468 views
Suggested answer LPC1857 (MCB1800) Setup CAN Bus Port Manually Latest yesterday by Andy Neil 2 replies 364 views