Getting Started

Cycle models are compiled directly from Arm RTL and retain complete functional and cycle accuracy. This enables you to confidently make architectural decisions, optimize performance or develop bare metal software.


Performance Optimization with Cycle Models

Instrumented for Analysis

Cycle Models are instrumented to enable detailed debug and analysis. CPU cores enable interactive debug with Arm Development Studio. Additionally, all registers and PMUs are visible along with information related to cache hits, pipeline statistics and much more.

Implementation level accuracy

Cycle Models are compiled directly from the implementation RTL and retain 100% of the functionality and cycle accuracy. Cycle Models can be used in SystemC simulation environments as well as RTL simulators.

Creation of Arm Cycle Models

Cycle Models are available 24 hours a day/7 days a week from Arm’s IP Exchange web portal. This portal enables users to access, configure, compile and manage their own models of Arm IP. Users are then emailed when their model is available for download

Get started with Cortex-M55 today within a familiar Cortex-M development environment

Compare performance, learn new instructions and optimize code with single programmer’s model for DSP/ML workloads.

More about Arm tools for Cortex-M55


CPU and Subsystem Portfolio

Arm releases models of our IP to lead partners at an early stage, so please contact us for more information on upcoming Cycle Models.

Faster Productivity with CPAKs


Arm System Exchange

In order to deliver a faster path to productivity, Arm offers an extensive library of prebuilt virtual systems featuring Cycle Models. These Cycle Performance Analysis kits are system models featuring multiple Cycle Models together with bare metal software or Linux level benchmarks. The complete selection of CPAKs is available for download from Arm System Exchange.

System IP Cycle Models

System IP Family
Interconnect NIC-400, CMN-600, CCI-550
Interrupt Controllers GIC-600, GIC-500
System Memory Management Units MMU-600
Memories BP-140, DMC-400

Cycle Models for DesignStart

Arm DesignStart makes innovation more accessible than ever. Whether you want to differentiate your product or conduct research, get started on a trusted, proven foundation with Arm IP and services. Cycle Models for DesignStart are included free of cost in the Cortex-M3 evaluation program to enable faster simulation and enhanced system visibility compared to RTL simulation.

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Community Forums

Answered osMutexWait() function before the RTX osKernelInitialize() 0 votes 414 views 9 replies Latest 2 days ago by Andy Neil Answer this
Answered Code jumps to cxsync1 in vectors.S?
  • Arm Development Studio
0 votes 639 views 2 replies Latest 2 days ago by DanijelDomazet Answer this
Answered Keil uVision compiling with API Issues
  • STM32F4DISCOVERY
  • Windows 10
  • api
  • uVision
  • Compilation error
0 votes 271 views 3 replies Latest 3 days ago by KevinM Answer this
Answered TTBR1_EL2 mmu translation information wrong when E2H=1 0 votes 1357 views 4 replies Latest 3 days ago by lemin9538 Answer this
Answered Breakpoints not working in C code, only in assembly?
  • Arm Development Studio
0 votes 1114 views 7 replies Latest 3 days ago by Danijel Answer this
Answered What happens to the Instructions already in pipeline when interrupt occurs ?
  • Software
  • Cortex-M0
  • Cortex-M0+
  • Interrupt
0 votes 373 views 6 replies Latest 4 days ago by 42Bastian Schick Answer this
Answered osMutexWait() function before the RTX osKernelInitialize() Latest 2 days ago by Andy Neil 9 replies 414 views
Answered Code jumps to cxsync1 in vectors.S? Latest 2 days ago by DanijelDomazet 2 replies 639 views
Answered Keil uVision compiling with API Issues Latest 3 days ago by KevinM 3 replies 271 views
Answered TTBR1_EL2 mmu translation information wrong when E2H=1 Latest 3 days ago by lemin9538 4 replies 1357 views
Answered Breakpoints not working in C code, only in assembly? Latest 3 days ago by Danijel 7 replies 1114 views
Answered What happens to the Instructions already in pipeline when interrupt occurs ? Latest 4 days ago by 42Bastian Schick 6 replies 373 views