Explore the Scalable Vector Extension (SVE)
Scalable Vector Extension (SVE) is a vector extension for AArch64 execution mode for the A64 instruction set of the Armv8-A architecture. Unlike other SIMD architectures, SVE does not define the size of the vector registers, but constrains it to a range of possible values, from a minimum of 128 bits up to a maximum of 2048 in 128-bit wide units. Therefore, any CPU vendor can implement the extension by choosing the vector register size that better suits the workloads the CPU is targeting. The design of SVE guarantees that the same program can run on different implementations of the instruction set architecture without the need to recompile the code.
Many instructions of the extension use predicate registers to mask the lanes for operating on partial vectors. The SVE instruction set also provides gather loads and scatter stores, truncating stores, and signed/unsigned extended loads.
The SVE2 (Scalable Vector Extension version two) is a superset of SVE and Neon, and allows for more function domains in data-level parallelism. SVE2 inherits the concept, vector registers, and operation principles of SVE.
For information about porting your codes to an SVE-enabled system, see the Porting to Arm SVE resources section.