Arm Socrates significantly reduces the time to select, configure and create Arm IP that is error free and ready for SoC integration.
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Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.
Intelligent interconnect construction and configuration of Arm IP
CoreLink interconnect creation
Modern system interconnects are highly configurable IP blocks that need to connect across multiple power and voltage domains to maximize SoC connectivity. Some of the problems facing interconnect design teams today include:
- SoCs are getting larger, with more components and greater connectivity.
- SoCs are composed of modular subsystems that bring reuse and timing closure issues.
- Interconnect backplane must offer multiple services:
- Lowest latency from CPU to memory
- QoS guarantees
- Clock and power management
Socrates addresses all of these issues and guides architects and designers through the configuration and creation of an optimized and viable CoreLink Interconnect. Socrates generates the interconnect µarchitecture, stitches it together, and validates the top level interconnect. Architects and designers can start with the high-level specification, generate the µArchitecture, and create the deliverables (RTL, design specification, testbench, and testcases). Architects and designers can visualize each stage of the design as well as validate the viability and quality using design rule checks.
CoreLink creation vastly reduces the time needed to implement and validate a complex on-chip AMBA® interconnect – down from several months to weeks.
Arm Socrates IP Tooling helps system designers to select and intelligently configure Arm IP, reducing the time to achieve integration ready IP to hours instead of days.
Socrates IP Tooling enables hardware, software, and verification teams to get the system performance they expect - through Arm IP that is configured, built, and integrated right first time. It is the only fully integrated solution for use with Arm System IP.
Socrates IP Tooling simplifies the configuration of Arm CoreLink System IP. Automatically create a CoreLink interconnect that is right first time.
Internal benchmarking has shown an 8x improvement in schedule when design teams use Socrates IP Tooling for the first time!
Arm IP selection configuration and build in minutes
Socrates includes the Arm IP catalog, which helps users select Arm IP and guides them through a construction, configuration and build in minutes.
Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.Arm training courses Open a support case
|Suggested answer||AXI4 master requirements for unaligned transactions (address v/s WSTRB)||0 votes||97 views||1 replies||Latest 12 hours ago by guimers8||Answer this|
|Not answered||TFT/LCD graphic contoller||0 votes||105 views||0 replies||Started 15 hours ago by levetop||Answer this|
|Not answered||Missing CoreSight components in /renensas/r8a77970.dtsi||0 votes||48 views||0 replies||Started yesterday by LWT||Answer this|
|Not answered||I am working on AXI vip and I am confused about where should I put logic about burst(FIXED,INCR,WRAP) can anybody give me direction ?||0 votes||66 views||0 replies||Started 2 days ago by pure||Answer this|
|Not answered||AMBA 5 CHI Coherance protocol details||0 votes||141 views||0 replies||Started 5 days ago by JO16||Answer this|
|Answered||Atomic access LDR/STR vs LDREX/STREX||0 votes||666 views||2 replies||Latest 6 days ago by EBB||Answer this|
|Suggested answer||AXI4 master requirements for unaligned transactions (address v/s WSTRB) Latest 12 hours ago by guimers8||1 replies 97 views|
|Not answered||TFT/LCD graphic contoller Started 15 hours ago by levetop||0 replies 105 views|
|Not answered||Missing CoreSight components in /renensas/r8a77970.dtsi Started yesterday by LWT||0 replies 48 views|
|Not answered||I am working on AXI vip and I am confused about where should I put logic about burst(FIXED,INCR,WRAP) can anybody give me direction ? Started 2 days ago by pure||0 replies 66 views|
|Not answered||AMBA 5 CHI Coherance protocol details Started 5 days ago by JO16||0 replies 141 views|
|Answered||Atomic access LDR/STR vs LDREX/STREX Latest 6 days ago by EBB||2 replies 666 views|