If the Xilinx UltraScale device is to be booted using the 'JTAG BOOT' mode of operation (see here), then this results in no Arm cores on the device being powered up.
In order to alleviate this, there are 2 scripts attached at the bottom of this page that may be of use for bare-metal development on either the Cortex-A53 (APU) or Cortex-R5 (RPU) cluster.

These might be used when developing bare-metal code on either the Xilinx UltraSCALE+ MPSoC or the Ultra96 target boards.

They perform the following operations :

  • write a Branch-to-self instruction to the reset vector
  • initialize the cores to an appropriate state (AARCH64 for the APU, Arm for the RPU)
  • bring them out of reset

This will leave the cores spinning at address 0xFFFF0000 which is the reset vector. The debugger can then take control of the processors.

Note that the DDR memory is not initialized as this normally done by u-boot. So the DDR initialization must be done in your application code.

There is 256KB of on-chip memory (OCM) in the range 0xFFFC0000 - 0xFFFFFFFF which can be used.



These scripts assume that the board is being booted in JTAG_BOOT mode, and that the cores in the given cluster are powered down.
A connection to at least 1 of the cores must be made in order to run these scripts.

The most applicable way to use the scripts is to add them to the 'Debug connection' tab as a script under the 'Run target script first' as shown below :


Arm DS screenshot showing where to add pre-connection scripts on Launcher panel


Once connected, you should find that the cores are halted at 0xFFFF0000, as shown below for the APU cores :

Arm DS screenshot showing connection to Ultrascale APU

 The script for the APU (Cortex-A53's) can be found here and for RPU (Cortex-R5's) here.

Note : Because the Cortex-A53's and Cortex-R5's are initialized using  different Arm architectures (AArch64 for the Cortex-A53, Arm mode for the Cortex-R5) the Branch-to-self instruction written to the location 0xFFFF0000 will only work for the core that it is intended for.