Getting Started

Neoverse reference designs provide useful resources with best practices on how to integrate a Neoverse compute subsystem within a larger SoC. These compute subsystems are targeted at addressing requirements for specific applications in the cloud-to-edge infrastructure markets including servers, edge compute nodes, networking-storage-security offloads, mezzanine cards, 5G stations and access points. 


Neoverse N1 hyperscale reference design

The Neoverse N1 hyperscale reference design details the integration of a high core count server-class SoC subsystem using the Neoverse N1 CPU, CMN-600 coherent mesh interconnect and supporting system IP.

Diagram for the Neoverse N1 hyperscale reference design.

  • 64x Neoverse N1 CPUs, each with 1MB private L2, providing 64 threads of parallel execution
  • 8x8 coherent mesh interconnect (CMN-600) configuration with 64MB of shared system level cache
  • CPUs connected directly to the mesh in dual-core configurations for lowest latency
  • 4x CCIX links for multi-socket, chiplets and accelerator attached configurations
  • 8x memory channels supporting DDR4-3200
  • GIC-600 and CoreSight SoC-400 interfacing over the mesh
  • MMU-600 system MMU and NIC-450 non-coherent interconnect integration with PCIe Gen4 support
  • Fully compliant with Arm ServerReady 1.0 specification

Neoverse N1 edge reference design

The Neoverse N1 edge reference design details the integration of a moderate core count edge server SoC subsystem with the Neoverse N1 CPU and CMN-600 mesh interconnect.

Neoverse N1 Edge Reference Design diagram 

  • 8x Neoverse N1 CPUs, each with 512kB private L2, providing 8 threads of parallel execution
  • 4x2 CMN-600 configuration with 8MB of shared system level cache
  • CPUs are connected to the mesh through quad-core clusters with 2MB shared L3
  • 4x CCIX links to support chiplet and accelerator attached configurations
  • 2x memory channels supporting DDR4-3200
  • GIC-600 generic interrupt controller and CoreSight SoC-400 debug and trace IP interfacing over the mesh
  • MMU-600 system MMU and NIC-450 non-coherent interconnect integration with PCIe Gen4 support
  • Fully compliant with Arm ServerReady 1.0 specification

Neoverse E1 edge reference design

The Neoverse E1 edge reference design details the integration of a moderate core count high data throughput SoC subsystem with the Noeverse E1 CPU and CMN-600 mesh interconnect.

Neoverse E1 Edge Reference Design diagram 

  • 16x Neoverse E1 CPUs, each with 256kB private L2, providing 32 threads of parallel execution
  • 4x2 CMN-600 mesh configuration with 8MB of shared system level cache
  • CPUs are connected to the mesh through octa-core clusters with 2MB shared L3
  • 4x CCIX links to support chiplet and accelerator attached configurations
  • 2x memory channels supporting DDR4-3200
  • GIC-600 generic interrupt controller and CoreSight SoC-400 debug and trace IP interfacing over the mesh
  • MMU-600 system MMU and NIC-450 non-coherent interconnect integration with PCIe Gen4 support
  • Fully compliant with Arm ServerReady 1.0 specification

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Not answered Where do I find presentations and photos from SC'18? Started 1 years ago by John Linford 0 replies 4570 views
Suggested answer Can't download code to address 0 on STM32F091RC using uVision Latest 8 hours ago by Westonsupermare Pier 2 replies 167 views
Suggested answer Cortex A9 MMU Latest 11 hours ago by deas 10 replies 1802 views
Not answered Include source file in DS 2020 Started 12 hours ago by Brittany_ruth 0 replies 31 views
Not answered communication Started 21 hours ago by jishan33333 0 replies 51 views
Suggested answer initialisation of DRAM ECC with Cortex A9 CPU Latest yesterday by 42Bastian Schick 3 replies 372 views