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New terms for the Arm Glossary

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List of terms

3A
The combination of Auto White Balance, Auto Exposure, and Autofocus.
A32
The instruction set used by an Armv8 processor that is in AArch32 execution state. A32 is a fixed-width instruction set that uses 32-bit instruction encoding. It is compatible with the Armv7 Arm instruction set.
A32 instruction
An instruction executed by a core that is in AArch32 Execution state and A32 Instruction set state. A32 is a fixed-width instruction set that uses 32-bit instruction encodings. Previously, this instruction set was called the Arm instruction set.
A32 state
When a core is in the AArch32 Execution state, if it is in the A32 Instruction set state then it executes A32 instructions.
A64
The instruction set used by an Armv8 processor that is in AArch64 execution state. A64 is a fixed-width instruction set that uses 32-bit instruction encoding.
A64 instruction
The instruction set used by an ARMv8-A core that is in AArch64 Execution state. A64 is a fixed-width instruction set that uses 32-bit instruction encodings.
AAPCS
The Arm Architecture Procedure call Standard defines how registers and the stack are used for subroutine calls.
AArch32
The Arm 32-bit Execution state that uses 32-bit general purpose registers, and a 32-bit program counter (PC), stack pointer (SP), and link register (LR). AArch32 Execution state provides a choice of two instruction sets, A32 and T32. In implementations of versions of the Arm architecture before Armv8, and in the Arm R and M architecture profiles, execution is always in AArch32 state.
AArch64
The Arm 64-bit Execution state that uses 64-bit general purpose registers, and a 64-bit program counter (PC), stack pointer (SP), and exception link registers (ELR). AArch64 Execution state provides a single instruction set, A64. AArch64 state is supported only in the Armv8-A architecture profile.
AB
Auto Brightness is an optional feature in Assertive Display which calculates optimal backlight brightness, ignoring internal backlight settings.
ABI
Application Binary Interface. A collection of specifications, some open and some specific to the Arm architecture, that regulate the inter-operation of binary code in a range of execution environments for Arm processors. The base standard specifies those aspects of code generation that must conform to a standard that supports inter-operation. It is aimed at authors and vendors of C and C++ compilers, linkers, and runtime libraries.
abort model
Describes the changes to the core state when a Data Abort exception occurs. Different abort models behave differently with regard to load and store instructions that specify base register write-back.
ACBC
Assertive Content and Backlight Control is a histogram-based power reduction engine, a constituent part of Assertive Display.
ACE
The AXI Coherency Extensions (ACE) provide additional channels and signaling to an AXI interface to support system level cache coherency.
ACE interface
An AMBA AXI4 interface that includes full support for the ACE protocol. An ACE interface adds: *Signals to some of the AXI4 channels. *Channels to the AXI4 interface.
ACE protocol
The AXI Coherency Extensions protocol, that adds signals to an AMBA AXI4 interface, to support managing the coherency of a distributed memory system.
ACE-Lite interface
An ACE-Lite interface is used by master components that do not have hardware coherent caches, but are required to indicate if issued transactions could be held in the hardware coherent caches of other masters.
ACM
Adaptive Content Management describes the entire video content pipeline of Assertive Display.
AD
Assertive Display is an advanced display management core incorporating backlight and content enhancement and power saving.
adaptive clocking
A technique where the debug interface hardware sends out a clock signal and then waits for the returned clock before generating the next clock pulse. This technique enables the run control unit in the debug hardware to adapt to differing signal drive capabilities and differing cable lengths.
Adaptive Content Management
Adaptive Content Management describes the entire video content pipeline of Assertive Display.
ADC
Assertive Display Control describes the entire backlight pipeline of Assertive Display.
Address Space Identifier
Some Translation Lookaside Buffers (TLBs) store Address Space Identifiers (ASIDs) in each TLB entry. Each independent task, or process, has a separate address space, assigned a unique Address Space Identifier (ASID) by the Operating System. The ASID allows the core to move from one process to another (also known as a context switch) without having to invalidate TLB entries.
addressing mode
A method of generating the memory address that a load or store instruction uses. The addressing modes mechanism can generate values for data-processing instructions to use as operands. The ADI connects a debugger to a device. The ADI is used to access memory-mapped components in a system, such as processors and CoreSight components.
ADI
The ADI connects a debugger to a device. The ADI is used to access memory-mapped components in a system, such as processors and CoreSight components. The ADI protocol defines the physical wire protocols that are permitted, and the logical programmers model.
Advanced eXtensible Interface
An AMBA bus protocol that supports:*Separate phases for address or control and data. *Unaligned data transfers using byte strobes. *Burst-based transactions with only start address issued. *Separate read and write data channels. *Issuing multiple outstanding addresses. *Out-of-order transaction completion.*Optional addition of register stages to meet timing or repropagation requirements. The AXI protocol includes optional signaling extensions for low-power operation.
Advanced High-performance Bus
An AMBA bus protocol supporting pipelined operation, with the address and data phases occurring during different clock periods. This means the address phase of a transfer can occur during the data phase of the previous transfer. The AHB provides a subset of the functionality of the AMBA AXI protocol.
advanced Microcontroller Bus Architecture
The AMBA family of protocol specifications is the Arm open standard for on-chip buses. AMBA provides solutions for the interconnection and management of the functional blocks that make up a System-on-Chip (SoC). Applications include the development of embedded systems with one or more processors or signal processors and multiple peripherals.
Advanced SIMD
A feature of the Arm architecture that provides Single Instruction Multiple Data (SIMD) operations on a dedicated bank of registers. If an implementation also supports scalar floating-point instructions, the floating-point and Advanced SIMD instructions use a common register bank. Arm Neon technology provides the Advanced SIMD instructions, and therefore these are often called the Neon instructions.
AE
Auto Exposure is the automatic calculation of optimal sensor and lens settings prior to exposure, to control the brightness of an image.
AEL
A version of embedded Linux OS ported to the Arm architecture.
AF
Auto Focus is the automatic calculation and control of lens focus distance, which aims to maximize the sharpness of the image subject.
AG
Analog Gain is the electrical amplification of a signal, before the process of analog-to-digital conversion.
AHB
An AMBA bus protocol supporting pipelined operation, with the address and data phases occurring during different clock periods. This means the address phase of a transfer can occur during the data phase of the previous transfer. The AHB provides a subset of the functionality of the AMBA AXI protocol.
AHB Access Port
An optional component of the DAP that provides an AHB interface to an SoC. CoreSight supports access to a system bus infrastructure using the AHB Access Port (AHB-AP) in the Debug Access Port (DAP). The AHB-AP provides an AHB master port for direct access to system memory. Other bus protocols can use AHB bridges to map transactions. For example, you can use AHB to AXI bridges to provide AHB access to an AXI bus matrix.
AHB Trace Macrocell
A trace source that makes bus information visible. This information cannot be inferred from the processor using just a trace macrocell. HTM trace can provide: * An understanding of multi-layer bus utilization. *Software debug, for example, visibility of access to memory areas and data accesses. *Bus event detection for trace trigger or filters, and for bus profiling.
AHB-AP
An optional component of the DAP that provides an AHB interface to an SoC. CoreSight supports access to a system bus infrastructure using the AHB Access Port (AHB-AP) in the Debug Access Port (DAP). The AHB-AP provides an AHB master port for direct access to system memory. Other bus protocols can use AHB bridges to map transactions. For example, you can use AHB to AXI bridges to provide AHB access to an AXI bus matrix.
AHB-Lite
A subset of the full AMBA AHB protocol specification. It provides all of the basic functions required by the majority of AMBA AHB slave and master designs, particularly when used with a multi-layer AMBA interconnect.
ALS
An Ambient Light Sensor is a light measurement device often integrated into the front face of a display panel, such as in a mobile device or television.
Ambient Light
Ambient light is defined as being any light in the surroundings of a device that is not emitted by the device.
Ambient Light Sensor
An Ambient Light Sensor is a light measurement device often integrated into the front face of a display panel, such as in a mobile device or television.
Analog Gain
Analog Gain is the electrical amplification of a signal, before the process of analog-to-digital conversion.
AoU
Assumptions of Use (AoU) are requirements which must be handled by the system integrator or system developer, either by implementing the requirement in their custom design, or by providing justification for why the requirement is not applicable to their design.
APB
An AMBA bus protocol for ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. Using the APB to connect to the main system bus through a system-to-peripheral bus bridge can help reduce system power consumption.
APB Access Port
An optional component of the DAP that provides an AHB interface to an SoC. CoreSight supports access to a system bus infrastructure using the AHB Access Port in the Debug Access Port (DAP). The AHB-AP provides an AHB master port for direct access to system memory. Other bus protocols can use AHB bridges to map transactions. For example, you can use AHB to AXI bridges to provide AHB access to an AXI bus matrix.
APB-AP
An optional component of the DAP that provides an AHB interface to an SoC. CoreSight supports access to a system bus infrastructure using the AHB Access Port in the Debug Access Port (DAP). The AHB-AP provides an AHB master port for direct access to system memory. Other bus protocols can use AHB bridges to map transactions. For example, you can use AHB to AXI bridges to provide AHB access to an AXI bus matrix.
Application Binary Interface for the Arm Architecture
Application Binary Interface. A collection of specifications, some open and some specific to the Arm architecture, that regulate the inter-operation of binary code in a range of execution environments for Arm processors. The base standard specifies those aspects of code generation that must conform to a standard that supports inter-operation. It is aimed at authors and vendors of C and C++ compilers, linkers, and runtime libraries.
Application Processor Status Register
In AArch32 User mode, a restricted form of the CPSR.
APSR
In AArch32 User mode, a restricted form of the CPSR.
architecturally executed
An instruction is architecturally executed only if it would be executed in a simple sequential execution of the program. When such an instruction has been executed and retired, it has been architecturally executed. Any instruction that is treated as a NOP because it fails its condition code check, is an architecturally executed instruction. In a processor that performs Speculative execution, an instruction is not architecturally executed if the processor discards the result of the Speculative execution of that instruction.
Arm Debug Interface
The ADI connects a debugger to a device. The ADI is used to access memory-mapped components in a system, such as processors and CoreSight components. The ADI protocol defines the physical wire protocols permitted, and the logical programmers model.
Arm Embedded Linux
A version of embedded Linux OS ported to the Arm architecture.
Arm instruction
An instruction executed by a core that is in AArch32 Execution state and A32 Instruction set state. A32 is a fixed-width instruction set that uses 32-bit instruction encodings. Previously, this instruction set was called the Arm instruction set.
Arm profiler
A plug-in to the Arm Workbench Integrated Development Environment that provides non-intrusive analysis of embedded software over time, on targets running at frequencies which are typically as high as 250MHz. Targets can be Real-Time System Models (RTSMs) and hardware targets.
Arm state
When a core is in the AArch32 Execution state, if it is in the A32 Instruction set state then it executes A32 instructions.
Arm TrustZone technology
The hardware and software that enable the integration of enhanced security features throughout an SoC. In Armv6K, Armv7-A and Armv8-M, the Security Extensions implement the TrustZone hardware. In Armv8, EL3 incorporates the TrustZone hardware.
Arm Workbench IDE
Arm Workbench IDE is based around the Eclipse IDE, and provides additional features to support the Arm development tools that are provided in RVDS.
armar
An object file archiver tool, which might be included as part of a compiler toolchain or development environment that Arm provides. armar enables you to archive ELF object files into a library. See also armclang, armclang integrated assembler, armcc, armasm, armlink, fromelf.
armasm
An assembler, for legacy armasm syntax assembly language source files, which might be included as part of a compiler toolchain or development environment that Arm provides. The assembler produces object files containing machine code. See also armclang, armclang integrated assembler, armcc, armlink, fromelf, armar.
armcc
A compiler, for C and C++ language source files, which might be included as part of a compiler toolchain or development environment that Arm provides. The compiler can produce object files containing machine code or assembly language source files. See also armclang, armclang integrated assembler, armasm, armlink, fromelf, armar.
armclang
A compiler, for C and C++ language source files, which might be included as part of a compiler toolchain or development environment that Arm provides. The compiler can produce object files containing machine code or assembly language source files. This compiler is based on LLVM and Clang. See also armflang, armclang integrated assembler, armcc, armasm, armlink, fromelf, armar.
armclang integrated assembler
An assembler, for GNU syntax assembly source files, which might be included as part of a compiler toolchain or development environment that Arm provides. The assembler produces object files containing machine code. This assembler is based on LLVM and Clang. See also armclang, armcc, armasm, armlink, fromelf, armar.
armflang
A compiler, for Fortran language source files, which might be included as part of a compiler toolchain or development environment that Arm provides. The compiler can produce object files containing machine code or assembly language source files. This compiler is based on LLVM and Flang. See also armclang, armclang integrated assembler, armlink, fromelf, armar.
armlink
A linker, for combining object files and library files by placing code and data at specific addresses, which might be included as part of a compiler toolchain or development environment that Arm provides. The linker can produce executable images, partially linked object files, or shared object files. See also armclang, armclang integrated assembler, armcc, armasm, fromelf, armar.
ArtiGrid
A power routing scheme, also referred to as Over The Cell.
ASID
Some Translation Lookaside Buffers (TLBs) store Address Space Identifiers (ASIDs) in each TLB entry. Each independent task, or process, has a separate address space, assigned a unique Address Space Identifier (ASID) by the Operating System. The ASID allows the core to move from one process to another (also known as a context switch) without having to invalidate TLB entries.
Assertive Content and Backlight Control
Assertive Content and Backlight Control is a histogram-based power reduction engine, a constituent part of Assertive Display.
Assertive Display
Assertive Display is an advanced display management core incorporating backlight and content enhancement and power saving.
Assumptions of Use
Assumptions of Use (AoU) are requirements which must be handled by the system integrator or system developer, either by implementing the requirement in their custom design, or by providing justification for why the requirement is not applicable to their design.
ATB
An AMBA bus protocol for trace data. The ATB is a common bus used by the trace components to pass trace data in a system in a data-agnostic format. A trace device can use an ATB to share CoreSight capture resources.
ATB bridge
A synchronous ATB bridge provides a register slice that meets timing requirements by adding a pipeline stage. It provides a unidirectional link between two synchronous ATB domains. An asynchronous ATB bridge provides a unidirectional link between two ATB domains with asynchronous clocks. This means it connects components in different clock domains.
atomicity
Describes actions that appear to happen as a single operation. In the Arm architecture, atomicity refers to either single-copy atomicity or multi-copy atomicity. The Arm Architecture Reference Manuals define these forms of atomicity.
ATPG
Automated Test Pattern Generation: The process of using a specialized software tool to automatically generate manufacturing test vectors for an ASIC design.
authentication asynchronous bridge
Transfers authentication signals between two asynchronous clock domains.
authentication synchronous bridge
Transfers authentication signals between two synchronous clock domains.
Auto Brightness
Auto Brightness is an optional feature in Assertive Display which calculates optimal backlight brightness, ignoring internal backlight settings.
Auto Exposure
Auto Exposure is the automatic calculation of optimal sensor and lens settings prior to exposure, to control the brightness of an image.
Auto Focus
Auto Focus is the automatic calculation and control of lens focus distance, which aims to maximize the sharpness of the image subject.
Auto White Balance
Auto White Balance correction is the automatic equalization of color channels to correctly reproduce neutral tones, normally considered with respect to the color temperature in Kelvin.
Automatic Test Pattern Generation
Automated Test Pattern Generation: The process of using a specialized software tool to automatically generate manufacturing test vectors for an ASIC design.
AWB
Auto White Balance correction is the automatic equalization of color channels to correctly reproduce neutral tones, normally considered with respect to the color temperature in Kelvin.
AWIDE
Arm Workbench IDE is based around the Eclipse IDE, and provides additional features to support the Arm development tools that are provided in RVDS.
AXI
An AMBA bus protocol that supports:*Separate phases for address or control and data. *Unaligned data transfers using byte strobes. *Burst-based transactions with only start address issued. *Separate read and write data channels. *Issuing multiple outstanding addresses. *Out-of-order transaction completion.*Optional addition of register stages to meet timing or repropagation requirements. The AXI protocol includes optional signaling extensions for low-power operation.
AXI Coherency Extensions
The AXI Coherency Extensions (ACE) provide additional channels and signaling to an AXI interface to support system level cache coherency.
AXI low-power interface
The low-power interface is an optional extension to the AXI protocol that targets two different classes of peripherals: *Any peripheral that has no power-down sequence, and that can indicate when its clocks can be turned off. *Any peripheral that requires a power-down sequence, and that can have its clocks turned off only after it enters a low-power state. The peripheral requires an indication from a system clock controller to indicate when to initiate the power-down sequence, and must then signal when it has entered its low-power state.
back-annotation
The process of applying timing characteristics from the implementation process onto a model.
backlight
Backlight can refer to either the backlight of an LCD display, or more generally to the brightness of any emissive display.
banked register
A register that has multiple instances. A property of the state of the device determines which instance is in use. For example, the Security state might determine which instance is in use.
Base Platform Application Binary Interface
The Base Platform Application Binary Interface (BPABI) is the base standard for the interface between executable files, such as dynamic shared objects and DLLs, and the systems that execute them.
base porting layer
A platform-dependent base driver software component that communicates with the Mali GPU. For example, the base porting layer controls the Mali GPU registers. You implement, or port, the base porting layer onto different target platforms.
base register
A register specified by a load or store instruction that is used as the base value for the address calculation for the instruction. Depending on the instruction, an offset can be added to or subtracted from the base register value to form the address that is used for the memory access.
Base Standard Application Binary Interface
Application Binary Interface. A collection of specifications, some open and some specific to the Arm architecture, that regulate the inter-operation of binary code in a range of execution environments for Arm processors. The base standard specifies those aspects of code generation that must conform to a standard that supports inter-operation. It is aimed at authors and vendors of C and C++ compilers, linkers, and runtime libraries.
BCD file
In the context of RealView Debugger, a BCD file enables you to define the memory map and memory-mapped registers for a target development board or processor. Arm provides various BCD files with RVDS for Arm development boards.
beat
An alternative term for an individual transfer within a burst. For example, an INCR4 burst comprises four beats.
big-endian
In the context of the Arm architecture, big-endian is defined as the memory organization in which the least significant byte of a word is at a higher address than the most significant byte, for example: *A byte or halfword at a word-aligned address is the most significant byte or halfword in the word at that address. *A byte at a halfword-aligned address is the most significant byte in the halfword at that address.
BIST
BIST (Built-In-Self-Test)is a design technique in which parts of a circuit are used to test the circuit itself.
BL
The black level is the value of a pixel when it is not illuminated.
black level
The black level is the value of a pixel when it is not illuminated.
Board and Chip Definition file
In the context of RealView Debugger, a BCD file enables you to define the memory map and memory-mapped registers for a target development board or processor. Arm provides various BCD files with RVDS for Arm development boards.
board file
A debugger uses this term to refer to the top-level configuration file, normally called rvdebug.brd, that references one or more other configuration files. A board file contains:*The debug configuration (connection-level) settings.*References to the debug interface configuration file that identifies the targets on the development platform.*References to any Board and Chip Definition (BCD) files assigned to a Debug Configuration.
boundary scan chain
A boundary scan chain is made up of serially connected devices that implement boundary scan technology using a standard JTAG TAP interface. Each device contains at least one TAP controller containing shift registers that form the chain, connected between TDI and TDO, through which test data is shifted. A processor can contain several shift registers, enabling you to access selected parts of the device.
BPABI
The Base Platform Application Binary Interface (BPABI) is the base standard for the interface between executable files, such as dynamic shared objects and DLLs, and the systems that execute them.
branch folding
A technique where, on the prediction of a branch, the target instructions are completely removed from the instruction stream presented to the execution pipeline. Branch folding can significantly improve the performance of branches, and take the CPI for branches below one.
branch phantom
Branch target instructions speculatively executed, in parallel with the main instruction stream, as a result of branch folding.
branch prediction
The selection of a future execution path for instruction fetch. For example, after a branch instruction, the processor can choose to speculatively fetch either the instruction following the branch or the instruction at the branch target.
breakpoint
A debug event triggered by the execution of a particular instruction. It is specified by one or both of the address of the instruction and the state of the processor when the instruction is executed.
breakpoint unit
In the context of an Arm debugger, a unit in a Chained breakpoint that combines with other breakpoint units to create a complex hardware breakpoint. In an M-profile processor, a hardware debug component that can be part of the Flash Patch and Breakpoint unit.
BSABI
Application Binary Interface. A collection of specifications, some open and some specific to the Arm architecture, that regulate the inter-operation of binary code in a range of execution environments for Arm processors. The base standard specifies those aspects of code generation that must conform to a standard that supports inter-operation. It is aimed at authors and vendors of C and C++ compilers, linkers, and runtime libraries.
byte lane strobe
A signal that determines which byte lanes are active, or valid, in a data transfer. Each bit of this signal corresponds to eight bits of the data bus.
byte swizzling
Re-arranging the order of bytes in a word or halfword.
byte-invariant
In a byte-invariant system, the address of each byte of memory remains unchanged when switching between little-endian and big-endian operation. When a data item larger than a byte is loaded from or stored to memory, the bytes making up that data item are arranged into the correct order depending on the endianness of the memory access. The Arm architecture supports byte-invariant systems in Armv6 and later versions.
CABC
Content Adaptive Backlight Control is a general term for power reduction methods such as the Assertive Content and Backlight Control (ACBC).
Cacheable
A data storage method in which, if a memory location to be written is not in cache memory, a cache line is allocated for the memory. The value of that memory is then loaded into the cache from main memory, and the new value for the location is written to cache.
CADI
The debug control and inspection API to a fast model.
Canonical Frame Address
In Debug With Arbitrary Record Format (DWARF), this is an address on the stack specifying where the call frame of an interrupted function is located.
captive thread
Captive threads are all threads that can be brought under the control of RVDS. Special threads, called non-captive threads, are essential to the operation of Running System Debug (RSD) and so are not under debugger control.
cast out
A cache line selected to be discarded to make room for a replacement cache line. This is required because of a cache miss. How it is selected for eviction is processor-specific.
CFA
In Debug With Arbitrary Record Format (DWARF), this is an address on the stack specifying where the call frame of an interrupted function is located.
chained breakpoint
In the context of an Arm debugger, a unit in a Chained breakpoint that combines with other breakpoint units to create a complex hardware breakpoint. In an M-profile processor, a hardware debug component that can be part of the Flash Patch and Breakpoint unit.
chained tracepoint
In the context of an ARM debugger, a complex tracepoint that comprises multiple tracepoint units.
channel interface
In an ECT device, the channel interface is one of the interfaces on CTI.
CIM
Abbreviation for Configuration and Integration Manual
clock gating
One way to reduce energy usage in the core is to remove power, which removes both dynamic and static currents, or to stop the clock of the core, which removes dynamic power consumption only and is referred to as clock gating.
cluster
A cluster is a collection of cores, particularly having a shared cache.
CMM
In the context of an Arm debugger, a scripting language provided for compatibility with other debuggers. If you are writing new scripts, Arm recommends that you use the GNU Debugger (GDB) scripting commands because these offer more functionality in the Arm Debuggers.
coherence order
Data accesses from a set of observers to a byte in memory are coherent if accesses to that byte by the members of the set of observers are consistent with there being a single total order of all writes to that byte in memory by all members of the set of observers. This single total order of all writes to that byte is the coherence order for that byte.
coherent
Data accesses from a set of observers to a byte in memory are coherent if accesses to that byte by the members of the set of observers are consistent with there being a single total order of all writes to that byte in memory by all members of the set of observers. This single total order of all writes to that byte is the coherence order for that byte.
Cold reset
A Cold reset has the same effect as starting the processor by turning the power on. This clears main memory and many internal settings. Some program failures can lock up the core and require a Cold reset to restart the system.
Communications channel
The hardware used for communicating between the software running on the processor, and an external host, using the debug interface. When this communication is for debug purposes, it is called the Debug Communications Channel (DCC).
Condensed Reference Format
An Arm proprietary file format for specifying test vectors. Typically, Arm supplies a script to convert CRF format to Verilog Reference Format (VRF).
condition code check
The process of determining whether a conditional instruction executes normally or is treated as a NOP. For an instruction that includes a condition code field, that field is compared with the condition flags to determine whether the instruction is executed normally. For a T32 instruction in an IT block, the value of the ITSTATE register determines whether the instruction is executed normally.
condition code field
A four-bit field in an Arm instruction that specifies the condition under which the instruction executes.
condition flags
The condition flags are the N, Z, C, and V bits of PSTATE or of a Program Status Register (PSR).
conditional breakpoint
A breakpoint that has one or more condition qualifiers assigned. The breakpoint is activated when all assigned conditions are met, and either stops or continues execution depending on the action qualifiers that are assigned. The condition normally references the values of program variables that are in scope at the breakpoint location.
conditional execution
When a conditional instruction starts executing, if the condition code check returns TRUE, the instruction executes normally. Otherwise, it is treated as NOP.
CONSTRAINED UNPREDICTABLE
Where an instruction can result in UNPREDICTABLE behavior, the Arm architecture can specify a narrow range of permitted behaviors. This range is the range of CONSTRAINED UNPREDICTABLE behavior. All implementations that are compliant with the architecture must follow the CONSTRAINED UNPREDICTABLE behavior. However, software must not rely on any CONSTRAINED UNPREDICTABLE behavior. When CONSTRAINED UNPREDICTABLE appears in body text, it is always in SMALL CAPITALS.
context switch
The saving and restoring of computational state when switching between different threads or processes. Context switch describes any situation where the context is switched by an operating system and might or might not include changes to the address space.
Context synchronization event
A Context synchronization event is one of: *In all versions of the ARM architecture: - The execution of an ISB instruction that does not fail its condition code check. - The taking of an exception. - The return from an exception. *In addition, in ARMv8 - Exit from Debug state. - Executing a DCPS instruction. - Executing a DRPS instruction. The architecture requires a Context synchronization event to guarantee visibility of any change to a System register.
contrast ratio
The ratio between the absolute luminous levels of the brightest and darkest pixels simultaneously displayable on a display.
coprocessor
A processor, or conceptual processor, that supplements the main processor to carry out additional functions. In AArch32 Execution state, the Arm architecture defines an interface to up to 16 coprocessors, CP0-CP15. In Armv8, AArch32 state supports only conceptual coprocessors CP10, CP11, CP14, and CP15. In previous versions of the architecture, coprocessors CP0-CP7 are available for implementation defined features, and coprocessors CP8-CP15 are reserved for use by Arm. In all architecture versions for the A and R architecture profiles, in AArch32 state: CP15 instructions access the System registers. Some documentation describes this set of registers as the System Control Coprocessor. CP14 instructions access System registers for debug, trace, and execution environment features. The CP10 and CP11 instruction space is for floating-point and Advanced SIMD instructions if supported, including the instructions for accessing the floating-point and Advanced SIMD System registers.
core
The abstract machine defined in the Arm architecture, as documented in an Arm Architecture Reference Manual. A processing element (PE) implementation that is compliant with the Arm architecture must conform with the behaviors described in the corresponding Arm Architecture Reference Manual. Arm processor documentation usually describes a PE as a Core.
core module
In the context of an Arm Integrator development board, an add-on development board that contains an Arm processor and local memory. Core modules can run standalone, or can be stacked onto Integrator development boards.
core register
Processing registers used in AArch32 Execution state, comprising: 13 general-purpose registers, R0 to R12, that software uses for all data processing when using the base instruction set instructions. SP, the Stack Pointer, that can also be referred to as R13. LR, the Link Register, that can also be referred to as R14. PC, the Program Counter, that can also be referred to as R15. In some situations, software can use SP, LR, and PC for processing. The instruction descriptions include any constraints on the use of SP, LR, and PC.
CoreSight ECT
A modular system that supports the interaction and synchronization of multiple triggering events with an SoC. It comprises:*Cross Trigger Interface(CTI).*Cross Trigger Matrix (CTM).
CoreSight ETB
A Logic block that extends the information capture functionality of a trace macrocell.
CoreSight ETM
A hardware macrocell that, when connected to a processor, outputs trace information on a trace port. The ETM provides processor driven trace through a trace port compliant to the ATB protocol. An ETM always supports instruction trace, and might support data trace.
CoreSight STM
A trace source designed primarily for high-bandwidth trace of instrumentation embedded into software. This instrumentation is made up of memory-mapped writes to the STM, which carry information about the behavior of the software.
CoreSight TMC
Controls the capturing or buffering of trace that is generated by trace sources within a system. The TMC receives trace from an ATB interface and can be configured to perform one of the following: -Route the trace out over an AXI master interface, to allow trace to be captured in system memory or in other peripherals. -Capture the trace in a circular buffer in dedicated SRAM. -Buffer the trace in a First In First Out (FIFO) style, to smooth over peaks in trace bandwidth.
Cortex Microcontroller Software Interface Standard
The Cortex Microcontroller Software Interface Standard (CMSIS) defines a common way to access peripheral registers or define exception vectors. CMSIS is name of the core exception vectors, and a device-independent interface for RTOS kernels, including a debug channel.
CPAK
Cycle Model Performance Analysis Kit. Pre-built, ready-to-simulate virtual systems that include models of Arm IP plus software.
CPI
The average number of clock cycles per instruction for a program or program fragment. It is the multiplicative inverse of instructions per cycle. You can use this value to compare the performance of different processors that implement the same instruction set. The lower the value, the better the performance.
CPSR
In AArch32 state, the register that holds the current program status.
CRF
An Arm proprietary file format for specifying test vectors. Typically, Arm supplies a script to convert CRF format to Verilog Reference Format (VRF).
Cross Trigger Interface
Part of an Embedded Cross Trigger (ECT) device. In an ECT, the CTI provides the interface between a processor or ETM and the CTM.
Cross Trigger Matrix
Part of an Embedded Cross Trigger (ECT) device. In an ECT device, the CTM combines the trigger requests generated by CTIs and broadcasts them to all CTIs as channel triggers.
cross-path blocking
Cross-path blocking occurs when a divergent node has congestion on one of its output nodes which blocks bus traffic to its other output nodes.
CTI
Part of an Embedded Cross Trigger (ECT) device. In an ECT, the CTI provides the interface between a processor or ETM and the CTM.
CTM
Part of an Embedded Cross Trigger (ECT) device. In an ECT device, the CTM combines the trigger requests generated by CTIs and broadcasts them to all CTIs as channel triggers.
Current Program Status Register
In AArch32 state, the register that holds the current program status.
Cworst
PVT corner indicating the worst or maximum capacitance.
Cycle Model
Model of Arm IP that provides a cycle-accurate programmer’s view for virtual prototyping.
Cycle Model Studio
Arm GUI that uses the Cycle Model Compiler to compile RTL into a Cycle Model for various simulation environments.
Cycles Per Instruction
The average number of clock cycles per instruction for a program or program fragment. It is the multiplicative inverse of instructions per cycle. You can use this value to compare the performance of different processors that implement the same instruction set. The lower the value, the better the performance.
DA
Debug Agent: In the RealView Debugger, the debug agent provides target-side support for Running System Debug (RSD). The debug agent can be a thread or be built into the RTOS. The debug agent and RealView Debugger communicate with each other using the DCC. This passes data between the debugger and the target using a hardware debug interface, without stopping the program or entering debug state. -or- Design Assurance, or Design Automation - Design Assurance = Validation; Design Automation = in-house EDA automation infrastructure
DAP
In an external debugger, a block that acts as a master on a system bus and provides access to the target.
DAPBUS interconnect
The DAPBUS interconnect connects a Debug Port (DP) to the Access Ports (APs) in a CoreSight DAP.
Data Abort
An indication to the core of an attempted data access that is not permitted. The Data Abort might be generated by access permission checks performed by the memory system on the core, or might be signaled by the memory system.
data breakpoint
In the context of the ARM debugger, a hardware breakpoint that activates when an access to a specified location meets a set of specified conditions. The conditions can include a check for a specific data value being accessed at the given location.
data cache
A cache used for only the storing of data.
data side
The processor logic responsible for the movement and processing of data.
Data Watchpoint and Trace unit
The Data Watchpoint and Trace (DWT) unit is an optional debug unit that provides watchpoints, data tracing, and system profiling for the processor.
data-active write transaction
A transaction that has completed the address transfer or leading write data transfer, but has not completed all its data transfers.
DBGTAP
A debug control and data interface based on IEEE 1149.1 JTAG Test Access Port (TAP). The interface has four or five signals.
DCC
A channel that carries data between a debugger and debug logic in the target processor. It can do this without stopping the program flow or causing entry to Debug state, but can also be used when the target is in Debug state. The DCC is part of the debug register interface of the target.
DDK
Driver Development Kit.
Debug Access Port
In an external debugger, a block that acts as a master on a system bus and provides access to the target.
debug agent
Debug Agent: In the RealView Debugger, the debug agent provides target-side support for Running System Debug (RSD). The debug agent can be a thread or be built into the RTOS. The debug agent and RealView Debugger communicate with each other using the DCC. This passes data between the debugger and the target using a hardware debug interface, without stopping the program or entering debug state. -or- Design Assurance, or Design Automation - Design Assurance = Validation; Design Automation = in-house EDA automation infrastructure
Debug and Trace Services Layer
Arm Debugger Debug and Trace Services Layer. Software layer that sits between the debugger and the RDDI target access API.
Debug Communications Channel
A channel that carries data between a debugger and debug logic in the target processor. It can do this without stopping the program flow or causing entry to Debug state, but can also be used when the target is in Debug state. The DCC is part of the debug register interface of the target.
debug configuration
In the context of an Arm debugger, a debug configuration defines a debugging environment for the development platform that is accessed through a particular debug interface. Multiple debug configurations can be created for a debug interface, each providing a separate debugging environment to different development platforms, or different debugging environments to the same development platform.All debug configurations are stored in the main debugger board file. Each configuration might reference one or more BCD files.
debug event
A debug event is some part of the process being debugged that causes the system to notify the debugger. Debug events can be synchronous or asynchronous.
debug illusion
The view of the software being debugged that a debugger presents to its user. The features of the debug illusion include:*Mapping between assembler code and source code, including displaying assembler and source code simultaneously if required.*Support for source-level stepping and breakpoints.*Visibility of the source-level function call stack, even when called functions are generated inline.*Display of variable values and structure field values, even when these values migrate between various locations. This includes displaying registers and the stack.
debug interface
In the context of RealView Debugger, the debug interface identifies the targets on your development platform, and provides the mechanism that enables RealView Debugger to communicate with those targets. The debug interface corresponds directly to a piece of hardware or a software simulator.
Debug Test Access Port
A debug control and data interface based on IEEE 1149.1 JTAG Test Access Port (TAP). The interface has four or five signals.
DEBUG_RECOV
Short name for the Debug recovery power mode that can apply to the cores or the DSU.
DebugBlock
The DebugBlock combines the functions, registers, and interfaces for debugging the DSU while the cores and cluster are powered down. Therefore, this component is separate from the cluster and in a separate power domain.
Default NaN mode
In floating-point operation, a mode in which all operations that result in a NaN return the default NaN, regardless of the cause of the NaN result. This mode is compliant with the IEEE 754 standard but implies that all information contained in any input NaNs to an operation is lost.
defective pixel
A faulty pixel which does not perform correctly, either a hot (white) pixel or dead (black) pixel.
denormalized value
The IEEE 754-2008 standard term for a floating-point operand with a zero exponent and a nonzero fraction field. Arm documentation describes these operands as denormal or denormalized, as defined by the IEEE 754-1985 standard.
Design for Test
Design for Test (DFT) are hardware product design techniques specifically employed to ensure that a hardware product is testable.
Design Simulation Model
A functional simulation model of the device that is derived from the RTL but that does not reveal its internal structure. The DSM does not model any features added during synthesis such as internal scan chains.
Development Studio 5
The suite of software development tools, together with supporting documentation and examples, that enable you to write and debug applications for the Arm family of processors. DS-5 supersedes RealView Development Suite.
Device Validation Suite
A set of tests to check the functionality of a device against that defined in the Technical Reference Manual.
DFT
Design for Test (DFT) are hardware product design techniques specifically employed to ensure that a hardware product is testable.
Digital Gain
Digital gain describes the multiplication of pixel value after analog-to-digital conversion.
Digital Image Stabilization
The process by which image blur that is caused by camera movement is removed using digital filters.
direct read
When an instruction uses a System register value to establish operating conditions, that use of a System register is an indirect read of that System register.
direct write
Occurs when the contents of a register are updated by some other mechanism than a direct write.
Direct-mapped cache
A one-way set-associative cache. Each cache set consists of a single cache line, so cache look-up selects and checks a single cache line.
DIS
The process by which image blur that is caused by camera movement is removed using digital filters.
Display Calibration Unit
The display calibration unit is responsible for calibrating colors and brightness tones in a display.
DNM
A value that must not be altered by software. These fields read as UNKNOWN values, and must only be written with the value read from the same field on the same processor.
Do-Not-Modify
A value that must not be altered by software. These fields read as UNKNOWN values, and must only be written with the value read from the same field on the same processor.
doubleword
A 64-bit data item. Doublewords are normally at least word-aligned in Arm systems.
doubleword-aligned
A data item having a memory address that is divisible by eight.
draw mode
In the context of graphics processing, one of the different ways to specify the primitives to draw. These different ways are called draw modes. The primitives can be specified individually or as a connected strip or fan. They can also be either:non-indexed, meaning that vertices are passed in a vertex array and processed in order. indexed, meaning that vertices are passed as indices into a vertex array.
DRC
Dynamic range compression describes any method which reduces the digital range needed to represent captured tones in an image.
DS-5
The suite of software development tools, together with supporting documentation and examples, that enable you to write and debug applications for the Arm family of processors. DS-5 supersedes RealView Development Suite.
DSM
A functional simulation model of the device that is derived from the RTL but that does not reveal its internal structure. The DSM does not model any features added during synthesis such as internal scan chains.
DSU
The DynamIQ Shared Unit (DSU) comprises the L3 memory system, control logic, and external interfaces to support a DynamIQ cluster. The DynamIQ cluster microarchitecture integrates one or more cores with the DSU to form a cluster that is implemented to a specified configuration.
DTM
In the context of physical IP, a data timing module that synchronizes incoming and outgoing data. The DTM is a component of PHY to include I/Os and PLL.
DTSL
Arm Debugger Debug and Trace Services Layer. Software layer that sits between the debugger and the RDDI target access API.
DVS
A set of tests to check the functionality of a device against that defined in the Technical Reference Manual.
Dynamic Range Compression
Dynamic range compression describes any method which reduces the digital range needed to represent captured tones in an image.
DynamIQ Shared Unit
The DynamIQ Shared Unit (DSU) comprises the L3 memory system, control logic, and external interfaces to support a DynamIQ cluster. The DynamIQ cluster microarchitecture integrates one or more cores with the DSU to form a cluster that is implemented to a specified configuration.
Early-Z
The Early-Z system checks that the depth of the pixel being processed is not already occupied by a nearer pixel. If it is occupied, it does not execute the fragment shader. Z testing typically happens after the fragment shader, however usually this shader is the most computationally expensive so should be avoided if the fragment is not visible in the scene.
ECC
ECC is the abbreviation for Error Correcting Code.
Eclipse for DS-5
Eclipse for DS-5 is based around the Eclipse IDE, and provides additional features to support the Arm development tools that are provided in DS-5.
ECT
A modular system that supports the interaction and synchronization of multiple triggering events with an SoC. It comprises:*Cross Trigger Interface(CTI).*Cross Trigger Matrix (CTM).
EGL
A standardized set of functions that communicate between graphics software, such as OpenGL ES or OpenVG drivers, and the platform-specific windowing system that displays the image.
ELP
Abbreviation for Enhanced Lead Partner
ELR
In AArch64 state, there is a dedicated LR for each implemented Exception level, called the Exception Link Register (ELR) for that Exception level, for example, ELR_EL1. The Exception Link Register holds the exception return address.
EMA
Extra Margin Adjustment -- add delay for extra margin during memory operation to account for manufacturing yield changes.
embedded assembler
Embedded assembler is a compiler feature that enables writing a C or C++ function entirely using assembly instructions, from within a C or C++ source language file.
Embedded Cross Trigger
A modular system that supports the interaction and synchronization of multiple triggering events with an SoC. It comprises:*Cross Trigger Interface(CTI).*Cross Trigger Matrix (CTM).
Embedded Trace Buffer
A Logic block that extends the information capture functionality of a trace macrocell.
Embedded Trace Macrocell
A hardware macrocell that, when connected to a processor, outputs trace information on a trace port. The ETM provides processor driven trace through a trace port compliant to the ATB protocol. An ETM always supports instruction trace, and might support data trace.
EmbeddedICE logic
An on-chip logic block that provides TAP-based debug support for an Arm processor. It is accessed through the DAP on the Arm processor.
EmbeddedICE-RT
Hardware provided by an Arm processor to aid debugging in real-time.
Embedded-System Graphics Library
A standardized set of functions that communicate between graphics software, such as OpenGL ES or OpenVG drivers, and the platform-specific windowing system that displays the image.
emulator
In the context of target connection hardware, an emulator provides an interface to the pins of a real processor. It emulates the pins to the external world, and enables you to control or manipulate signals on those pins.
endianness
The scheme that determines the order of the successive bytes of data in a larger data structure when that structure is stored in memory.
ESSL
A programming language this is used to create custom shader programs that can be used in a programmable pipeline, on the Mali GPU. You can also use pre-defined library shaders, which are written in ESSL.
ESSL compiler
The compiler that translates shaders that are written in ESSL, into binary code for the shader units in the Mali GPU. There are two versions of the ESSL compiler: -the on-target compiler -the offline compiler.
ETB
A Logic block that extends the information capture functionality of a trace macrocell.
ETM
A hardware macrocell that, when connected to a processor, outputs trace information on a trace port. The ETM provides processor driven trace through a trace port compliant to the ATB protocol. An ETM always supports instruction trace, and might support data trace.
ETV
Extended Target Visibility enables RealView Debugger to access features of the underlying target such as chip-level information provided by the hardware manufacturer or SoC designer.
event asynchronous bridge
A fixed component that synchronizes events on a single channel from the slave domain to the master domain. In addition, the event acknowledge from the master domain is synchronized and signaled to the slave domain.
Exception level
In the ARMv8 architecture, a program executes at one of four Exception levels. In AArch64, the Exception level determines the level of execution privilege. Exception levels provide a logical separation of software execution privilege that applies across all operating states of the ARMv8 architecture. System software determines the Exception level, and therefore the level of privilege, at which software runs.
Exception Link Register
In AArch64 state, there is a dedicated LR for each implemented Exception level, called the Exception Link Register (ELR) for that Exception level, for example, ELR_EL1. The Exception Link Register holds the exception return address.
Exception model
exception vector
A fixed address that contains the address of the first instruction of the corresponding exception handler.
exceptional state
In an Armv7 implementation that includes a VFP subarchitecture, in floating-point operation, if the floating-point hardware detects an exceptional condition, the Arm floating-point implementation sets the FPEXC bit and loads a copy of the exceptional instruction to the FPINST register. When in the exceptional state, the issue of a trigger instruction to the floating-point extension causes a bounce.
execution vehicle
A part of the debug target interface that processes requests from the client tools to the target.
execution view
In Arm compiler toolchains, execution view describes the memory map layout by showing each region and section, in the image, in terms of the addresses where the regions and sections are located during execution.
explicit access
A read from memory, or a write to memory, generated by a load or store instruction executed by the core. Reads and writes generated by hardware translation table accesses are not explicit accesses.
Extended Target Visibility
Extended Target Visibility enables RealView Debugger to access features of the underlying target such as chip-level information provided by the hardware manufacturer or SoC designer.
eXtensible Verification Component
Extensible Verification Component. A model that provides system or device stimulus and monitor responses.
fail-safe
Fail-safe is a feature available in the I/O library.
Fast Context Switch Extension
Before Armv8, an extension to the Arm architecture that modifies the behavior of the memory system. It enables multiple programs running on the core to use identical address ranges, while ensuring that the addresses they present to the rest of the memory system differ. From Armv6, ARM deprecates use of the FCSE. The FCSE is optional in Armv7, and obsolete from the Armv7 Multiprocessing Extensions.
Fast Model
Instruction-accurate model for early software development on Arm systems. You can use the model, together with Arm profiler and an Arm debugger, to optimize and debug your applications early in the development cycle.
Fast Models library
Instruction-accurate model for early software development on Arm systems. You can use the model, together with Arm profiler and an Arm debugger, to optimize and debug your applications early in the development cycle.
Fast Models portfolio
Instruction-accurate model for early software development on Arm systems. You can use the model, together with Arm profiler and an Arm debugger, to optimize and debug your applications early in the development cycle.
Fastline
An MTI trace plug-in that allows you to instrument Fast Models for analysis in Streamline.
FCSE
Before Armv8, an extension to the Arm architecture that modifies the behavior of the memory system. It enables multiple programs running on the core to use identical address ranges, while ensuring that the addresses they present to the rest of the memory system differ. From Armv6, ARM deprecates use of the FCSE. The FCSE is optional in Armv7, and obsolete from the Armv7 Multiprocessing Extensions.
Field Programmable Gate Array
An array of configurable logic blocks with configurable interconnects which can be used to reprogram a desired application and test the application's functional requirements.
Fingrid
Fingrid is the short form of FinFET grid.
FIQ
FIQ interrupt. nFIQ is one of two interrupt signals on many Arm processors.
Flash Patch and Breakpoint
In an Arm M-profile processor, an FPB can: -Remap sections of ROM, typically flash memory, to regions of RAM. -Set breakpoints on code in ROM. It can be used for debug, and to provide a code or data patch to an application that requires field updates to a product ROM.
flat address mapping
A memory system where the physical address for every access is equal to its virtual address. Sometimes called a flat mapping.
floating-point unit
A floating-point unit (FPU), also known as a math coprocessor) is specially designed to carry out operations on floating-point numbers. Typical operations are addition, subtraction, multiplication and division.
flush to-zero
In floating-point operation, a mode that optimizes the performance of some floating-point algorithms by replacing the denormalized operands and intermediate results with zeros, without significantly affecting the accuracy of their final results. Using the Flush to Zero mode is a deviation from IEEE 754.
Flush-to-zero mode
In floating-point operation, a special processing mode that optimizes the performance of some floating-point algorithms by replacing the denormalized operands and intermediate results with zeros, without significantly affecting the accuracy of their final results.
FOM data
FOM data is a comparison of the normalized performance and leakage characteristics among different standard cell libraries available within Arm POP IP.
formatter
In an ETB or TPIU, an internal input block that embeds the trace source ID in the data to create a single trace stream.
FPB
In an Arm M-profile processor, an FPB can: -Remap sections of ROM, typically flash memory, to regions of RAM. -Set breakpoints on code in ROM. It can be used for debug, and to provide a code or data patch to an application that requires field updates to a product ROM.
FPGA
An array of configurable logic blocks with configurable interconnects which can be used to reprogram a desired application and test the application's functional requirements.
fragment processor
In the context of graphics processors, a programmable processor that performs rendering operations to produce a final image for display. The fragment processor receives completed vertex data from the vertex processor and then runs fragment shader programs. The fragment processor was originally called the pixel processor.
fragment shader
A program running on the fragment processor that calculates the color and other characteristics of each fragment.
fragment thread creator
In a Mali GPU, a functional block that creates and issues threads to the tri-pipe processing unit pipeline. It is used for all fragment jobs output from the tiler.
frame buffer
A frame buffer is a portion of RAM containing a bitmap that is driven to a video display from a memory buffer containing a complete frame of data. The information in the memory buffer typically consists of color values for every pixel on the screen.
fromelf
An object file format conversion tool, which might be included as part of a compiler toolchain or development environment that Arm provides. fromelf enables you to convert ELF images and object files, and to display information about those files. See also armclang, armclang integrated assembler, armcc, armasm, armlink, armar.
FTC
In a Mali GPU, a functional block that creates and issues threads to the tri-pipe processing unit pipeline. It is used for all fragment jobs output from the tiler.
FULL_RET
Short name for the Core dynamic power mode for cores and for the Full retention power mode for some DSUs.
fully-associative cache
A cache that has only one cache set, that consists of the entire cache.
FUNC_RET
Short name for the Functional retention power mode that typically only applies to the DSU.
general-purpose register
Processing registers used in AArch32 Execution state, comprising: 13 general-purpose registers, R0 to R12, that software uses for all data processing when using the base instruction set instructions. SP, the Stack Pointer, that can also be referred to as R13. LR, the Link Register, that can also be referred to as R14. PC, the Program Counter, that can also be referred to as R15. In some situations, software can use SP, LR, and PC for processing. The instruction descriptions include any constraints on the use of SP, LR, and PC.
Generic Interrupt Controller
A Generic Interrupt Controller (GIC) is an exclusive block of IP that performs critical tasks of interrupt management, prioritization, and routing. GICs are primarily used for boosting processor efficiency and supporting interrupt virtualization. GICs are implemented based on Arm GIC architecture which has evolved from GICv1 to the latest version GICv3/v4. Arm has several multi-cluster CPU interrupt controllers that provide a range of interrupt management solutions for all types of Arm Cortex processor systems.
generic thread creator
In a Mali GPU, the Generic Thread Creator is a functional block that creates and issues threads to the tri-pipe processing unit pipeline. It is used for all non-fragment jobs, including vertex shading, geometry shading, and OpenCL jobs.
GIC
Abbreviation for Generic Interrupt Controller. A GIC is an exclusive block of IP that performs critical tasks of interrupt management, prioritization and routing. GICs are primarily used for boosting processor efficiency and supporting interrupt virtualization. GICs are implemented based on Arm GIC architecture which has evolved from GICv1 to the latest version GICv3/v4. Arm has a number of multi-cluster CPU interrupt controllers that provide a range of interrupt management solutions for all types of Arm Cortex processor systems.
GIC CPU interface
A common interrupt controller programming interface, defined by the GIC architecture.
G-POP
A POP that includes components for an Arm MALI graphics processor.
GPR
Used by a debugger to control powerup and powerdown of specific components within a CoreSight system.
GPU
Graphics Processing Unit: A hardware accelerator for graphics systems using OpenGL ES and OpenVG. The Mali-200,Mali-300, and Mali-400 MP GPUs comprise of a vertex processor and one or more fragment processors. Mali-T600 series GPUs consist of one or more shader cores that can execute vertex or fragment shaders.
granular power requester
Used by a debugger to control powerup and powerdown of specific components within a CoreSight system.
graphics application
A custom program that executes in the Mali graphics system and displays content in a frame buffer for transfer to a display.
graphics driver
A software library implementing OpenGL ES or OpenVG, using graphics accelerator hardware.
Graphics Processor Unit
Graphics Processing Unit: A hardware accelerator for graphics systems using OpenGL ES and OpenVG. The Mali-200,Mali-300, and Mali-400 MP GPUs comprise of a vertex processor and one or more fragment processors. Mali-T600 series GPUs consist of one or more shader cores that can execute vertex or fragment shaders.
GTC
In a Mali GPU, the Generic Thread Creator is a functional block that creates and issues threads to the tri-pipe processing unit pipeline. It is used for all non-fragment jobs, including vertex shading, geometry shading, and OpenCL jobs.
halfword
A 16-bit data item. Halfwords are normally halfword-aligned in Arm systems.
halfword-aligned
A data item having a memory address that is divisible by 2.
Halted System Debug
In the context of an ARM debugger, this means that a target can only be debugged when it is not running. With the target stopped, RealView Debugger presents OS awareness information by reading and interpreting target memory.
Halting debug
In Arm A-profile and R-profile processors, in AArch32 state, one of two mutually exclusive debug modes. When Halting debug is enabled, core execution halts when a breakpoint or watchpoint is encountered. You can use the debug interface to examine and alter all core state, memory, input and output locations.
HardFault
HardFault is the generic fault that exists for all classes of fault that cannot be handled by any of the other exception mechanisms.
hardware breakpoint
In the context of an Arm debugger, a unit in a Chained breakpoint that combines with other breakpoint units to create a complex hardware breakpoint. In an M-profile processor, a hardware debug component that can be part of the Flash Patch and Breakpoint unit.
HDR
High dynamic range describes an image in which methods have been used to artificially exceed the dynamic range of the sensor, for example, using multiple exposures.
Head-of-line blocking
In an interconnect, this occurs when a node prevents an important transaction from progressing because a less important transaction blocks the path to the same destination.
hierarchical tiler
In the context of a Mali GPU, the hierarchical tiler sorts all the primitives in the scene into a hierarchical list structure. These lists are then processed by the shader cores.
high registers
In AArch32 state, core registers R8-R12, SP, LR, and PC. Some T32 instructions cannot access these registers.
high vectors
In AArch32 state, one of two possible locations for exception vectors. The high vector address range is near the top of the address space, rather than at the bottom.
hint instruction
A hint instruction provides information that the hardware can take advantage of.
Hit-Under-Miss
A Hit-Under-Miss (HUM) buffer that means a memory access can hit in the cache, even though there has been a data miss in the cache.
HSD
In the context of an ARM debugger, this means that a target can only be debugged when it is not running. With the target stopped, RealView Debugger presents OS awareness information by reading and interpreting target memory.
HTM
A trace source that makes bus information visible. This information cannot be inferred from the processor using just a trace macrocell. HTM trace can provide: * An understanding of multi-layer bus utilization. *Software debug, for example, visibility of access to memory areas and data accesses. *Bus event detection for trace trigger or filters, and for bus profiling.
HUM
A Hit-Under-Miss (HUM) buffer that means a memory access can hit in the cache, even though there has been a data miss in the cache.
HVC
HyperVisor Call instruction used in both the Armv7 and Armv8 architectures. Used to generate a synchronous exception that is handled by a hypervisor running in EL2.
ICE Extension Unit
A hardware extension to the EmbeddedICE logic that provides more breakpoint units.
IDAU
The Arm®v8‑M architecture defines a mechanism whereby an implementation can define whether any particular address is exempt from checking, is NSC or Secure. If the ARMv8‑M Security Extension is included, then the internal Security Attribution Unit (SAU) or an external Implementation Defined Attribution Unit (IDAU) determines the Security state attributed to each address.
IEEE 1149.1
The IEEE Standard that defines the Test Access Port (TAP). Commonly referred to as JTAG. See IEEE Std 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture specification available from the IEEE Standards Association.
IEM
An energy manager solution consisting of both software and hardware components that function together to prolong battery life in an Arm processor-based device.
IGN
An abbreviation for Ignore, when describing the behavior of a register or memory access.
IGNORED
Indicates that the architecture guarantees that the bit or field is not interpreted or modified by hardware, meaning software can safely define how the bit is used.
iIntegrator
A range of Arm hardware development platforms. Core modules are available that contain the processor and local memory.
illegal instruction
Indicates an instruction that is not architecturally defined. It generates an Undefined Instruction exception.
image signal processor
An image signal processor, also called an image-processing engine, is a specialized digital signal processor that is used for image processing in digital cameras, mobile phones, or other devices.
immediate value
A value that is encoded directly in the instruction and used as numeric data when the instruction is executed. Many Arm and Thumb instructions can be used with an immediate argument.
IMPLEMENTATION DEFINED
Behavior that is not defined by the architecture, but is defined and documented by individual implementations.
Implementation Defined Attribution Unit
The Arm®v8‑M architecture defines a mechanism whereby an implementation can define whether any particular address is exempt from checking, is NSC or Secure. If the ARMv8‑M Security Extension is included, then the internal Security Attribution Unit (SAU) or an external Implementation Defined Attribution Unit (IDAU) determines the Security state attributed to each address.
IMPLEMENTATION SPECIFIC
In the context of Arm trace macrocells, behavior that is not architecturally defined, and might not be documented by an individual implementation. Used when there are a number of implementation options available and the option chosen does not affect software compatibility.
imprecise tracing
In an Arm trace macrocell, a filtering configuration where instruction or data tracing can start or finish earlier or later than expected. Most imprecise cases cause tracing to start or finish later than expected.
In-Circuit Emulator
A device that provides access to the signals of a circuit while that circuit is operating, and lets you moderate those signals.
index register
A register that is specified in some load or store instructions. The value of this register is used as an offset to be added to or subtracted from the base register value to form the virtual address that is sent to memory. Some instruction forms permit the index register value to be shifted before the addition or subtraction.
indirect read
When an instruction uses a System register value to establish operating conditions, that use of a System register is an indirect read of that System register.
indirect write
Occurs when the contents of a register are updated by some other mechanism than a direct write.
Input section
In Arm compiler toolchains, an input section is an individual section from an input object file. It contains code, initialized data, or describes a fragment of memory that is not initialized or that must be set to zero before the image can execute. armlink operates on input sections by grouping them into bigger building blocks called output sections and regions.
Instruction Abort
An indication to the core of an attempted instruction fetch that is not permitted. The Instruction Abort might be generated by access permission checks performed by the memory system on the core, or might be signaled by the memory system. An exception is taken only if the core attempts to execute the instruction. No exception is taken if the core does not execute an instruction that is attempted to fetch or prefetch from a faulting memory location. The AArch64 architecture definitions introduce the term Instruction Abort. Descriptions of AArch32 state use the term Prefetch Abort.
instruction breakpoint
In the context of an ARM debugger, a location in the image containing an instruction that, if executed, activates a breakpoint. The breakpoint activation can be delayed by assigning condition qualifiers, and subsequent execution of the image is determined by any actions assigned to the breakpoint.
instruction cache
A cache used for only the storing of instructions.
instruction set system model
In the context of RVDS, ISSM is a set of models that simulate the Arm Cortex family of processors. These models are provided with RVDS.
instruction side
The processor logic responsible for the fetching of instructions and providing them to the core.
Instruction Synchronization Barrier
An operation to ensure that any instruction that comes after the ISB operation is fetched only after the ISB has completed.
instrumentation trace
A component for debugging real-time systems through a simple memory-mapped trace interface. It provides printf-style debugging.
Instrumentation Trace Macrocell
Hard real-time debugging requires close interaction with the processor. Tracing provides a chronological picture of a system's inner workings up to, starting from or in the vicinity an event, mainly to guide a human in understanding a faulty program. For processors with Arm CoreSight (for example, Cortex-M3 and Cortex-M4), the Instrumentation Trace Macrocell (ITM) provides a lightweight, nonintrusive way to collect debug trace output.
Intelligent Energy Manager
An energy manager solution consisting of both software and hardware components that function together to prolong battery life in an Arm processor-based device.
intermediate physical address
In an implementation of virtualization, the intermediate physical address to which a Guest OS maps a virtual address.
Intermediate result
In a floating-point operation, an internal format that is used to store the result of a calculation before rounding. This format can have a larger exponent field and fraction field than the destination format.
internal scan chain
A series of registers connected together to form a path through a device, which is used during production testing to import test patterns into internal nodes of the device and export the resulting values.
interworking
Interworking enables a processor to automatically switch between A32 and T32 state when branching between A32 and T32 functions.
IPA
In an implementation of virtualization, the intermediate physical address to which a Guest OS maps a virtual address.
IRI
Interrupt Redistribution Infrastructure, one of two parts defined by the GICv3 architecture.
IRQ
IRQ interrupt. nIRQ is one of two interrupt signals on many Arm processors.
ISB
An operation to ensure that any instruction that comes after the ISB operation is fetched only after the ISB has completed.
ISP
An image signal processor, also called an image-processing engine, is a specialized digital signal processor that is used for image processing in digital cameras, mobile phones, or other devices.
ISSM
In the context of RVDS, ISSM is a set of models that simulate the Arm Cortex family of processors. These models are provided with RVDS.
IT block
In AArch32 state, a block of up to four instructions following a T32 IT (If-Then) instruction. Each instruction in the block is conditional. The condition for each instruction is either the same as or the inverse of the condition that is specified by the IT instruction.
Jazelle DBX
The Jazelle Extension technology is called Jazelle DBX.
Jazelle Extension
Some Arm processors before Armv8 included the Jazelle Extension, to provide hardware execution of some Java bytecodes in AArch32 state, as part of a Java Virtual Machine (JVM) implementation. From ARMv8, the architecture supports only an AArch32 Trivial Jazelle implementation, meaning a JVM must be implemented entirely in software. The Jazelle Extension technology is called Jazelle DBX.
Jazelle RCT
On an Arm processor, a modification of the T32 instruction set to make it a better target for code generated at runtime. This is also called the T32 Execution Environment (T32EE). From Armv8, Arm processors do not support Jazelle RCT.
Jazelle Runtime Compilation Target
On an Arm processor, a modification of the T32 instruction set to make it a better target for code generated at runtime. This is also called the T32 Execution Environment (T32EE). From Armv8, Arm processors do not support Jazelle RCT.
Jazelle state
In AArch32 state, in the Jazelle Instruction set state the core executes Java bytecodes as part of a Java Virtual Machine (JVM). From Armv8, ARM processors do not support Jazelle state.
Jazelle Technology Enabling Kit
A kit containing source code for integration with a Java Virtual Machine to enable Jazelle DBX on an Arm-based host platform.
JND
The minimum variation in brightness or color which can be detected by a typical human, according to standardized models.
job object
In the context of graphics processing, a Mali job system component that provides jobs with required content for Mali GPU execution.
job system back-end
In the context of graphics processing, a Mali job system component that shares some priority handling, but mainly requests jobs from queues and sends job requests to the Mali GPU.
Joint Test Action Group
An IEEE group that is focused on silicon chip testing methods. Many debug and programming tools use a Joint Test Action Group (JTAG) interface port to communicate with processors.
JTAG
An IEEE group that is focused on silicon chip testing methods. Many debug and programming tools use a Joint Test Action Group (JTAG) interface port to communicate with processors.
JTAG Access Port
An optional component of the DAP that provides debugger access to on-chip scan chains.
JTAG interface unit
In the context of Arm RealView tools, a protocol converter that converts low-level commands from RVDS debuggers into JTAG signals to the processor, for example to the EmbeddedICE logic and the ETM.
JTAG-AP
An optional component of the DAP that provides debugger access to on-chip scan chains.
JTAG-DP
In an external debugger, a block that acts as a master on a system bus and provides access to the target.
JTEK
A kit containing source code for integration with a Java Virtual Machine to enable Jazelle DBX on an Arm-based host platform.
Just Noticeable Difference
The minimum variation in brightness or color which can be detected by a typical human, according to standardized models.
K Virtual Machine
A small implementation of a Java Virtual Machine. It was originally derived from the Sun Spotless Virtual Machine.
KVM
A small implementation of a Java Virtual Machine. It was originally derived from the Sun Spotless Virtual Machine.
lef
Liberty Exchange Format (LEF) is an abstract view of a cell. It provides information such as PR boundary, pin positions, and metal layer information of a cell.
lib
Liberty file contains power and timing information for a cell.
little-endian
In the context of the Arm architecture, big-endian is defined as the memory organization in which the least significant byte of a word is at a higher address than the most significant byte, for example: *A byte or halfword at a word-aligned address is the most significant byte or halfword in the word at that address. *A byte at a halfword-aligned address is the most significant byte in the halfword at that address.
load view
In Arm compiler toolchains, load view describes the memory map layout by showing each region and section in the image, according to the addresses where the regions and sections are located when the image is loaded into memory, before execution starts.
load/store architecture
A processor architecture where data-processing operations only operate on register contents, not directly on memory contents. The Arm architecture is a Load/Store architecture.
low registers
In AArch32 state, core registers R0-R7. All T32 instructions can access these registers.
Low-Power Interface
An interface used for controlling the transitions between power modes.
makefile
A makefile is a special file, containing shell commands, that you create and name makefile (or Makefile depending upon the system). While in the directory containing this makefile, you will type make and the commands in the makefile will be executed. Typically the makefile provides one or more scripts that are used by the Unix make utility to determine which portions of a program (target) to compile.
Mali MMU
A full-featured Memory Management Unit (MMU) that is present on Mali GPUs.
MBIST
Abbreviation for Memory Built-In Self Test. The MBIST interface provides support for manufacturing testing of the memories embedded in a processor. MBIST is the industry-standard method of testing embedded memories. MBIST works by performing sequences of reads and writes to the memory based on test algorithms.
MEM_RET
Short name for the Memory retention power mode that typically only applies to the DSU.
Memory Built-In Self Test
The Memory Built-In Self Test (MBIST) interface provides support for manufacturing testing of the memories embedded in a processor. MBIST is the industry-standard method of testing embedded memories. MBIST works by performing sequences of reads and writes to the memory based on test algorithms.
memory coherency
A memory system is coherent if the value read by a data read or instruction fetch is always the value that was most recently written to that location. Memory coherency is difficult when the memory system includes multiple possible physical locations, such as main memory and at least one of a write buffer or one or more caches.
Memory Management Unit
(MMU) Provides detailed control of the memory system. Most of the control uses translation tables that are held in memory. An MMU is the major component of an Arm Virtual Memory System Architecture (VMSA).
Memory Protection Unit
A hardware unit that controls a limited number of protection regions in memory. An MPU is the major component of an Arm Protected Memory System Architecture (PMSA).
Micro Trace Buffer
The Micro Trace Buffer provides a simple execution trace capability to M-series processors. The MTB provides a lighter option for instruction trace requirements for software development. Unlike the Embedded Trace Macrocell(ETM) or the Program Trace Macrocell(PTM) trace solutions, the MTB does not require dedicated trace connection. However, the amount of trace history provided by the MTB is limited by the size of SRAM allocated for trace operations.
Microcontroller Development Kit
Keil® MDK is the most comprehensive software development solution for Arm®-based microcontrollers and includes all components that you need to create, build, and debug embedded applications.
MMU
(MMU) Provides detailed control of the memory system. Most of the control uses translation tables that are held in memory. An MMU is the major component of an Arm Virtual Memory System Architecture (VMSA).
model manager
A software control manager that handles the event transactions between the model and simulator.
Modified Virtual Address
The address produced by the FCSE that is sent to the rest of the memory system to be used in place of the normal virtual address. If the FCSE is absent or disabled, the MVA and the Virtual Address (VA) have the same value. From Armv6, Arm deprecates any use of the FCSE. The FCSE is optional in the unextended Armv7 architecture, and obsolete from the introduction of the Multiprocessing Extensions.
Monitor debug
In Arm A-profile and R-profile processors, in AArch32 state, one of two mutually exclusive debug modes. When Monitor debug is enabled, a debug event generates a debug exception, that is taken as a Prefetch Abort or Data Abort exception. Breakpoints and watchpoints are examples of debug events.
MPCore
An integrated Symmetric Multiprocessor System (SMP) or Asymmetric Multiprocessor System (AMP) with multiple cores in a single cluster.
MPU
A hardware unit that controls a limited number of protection regions in memory. An MPU is the major component of an Arm Protected Memory System Architecture (PMSA).
MTB
The Micro Trace Buffer provides a simple execution trace capability to M-series processors. The MTB provides a lighter option for instruction trace requirements for software development. Unlike the Embedded Trace Macrocell(ETM) or the Program Trace Macrocell(PTM) trace solutions, the MTB does not require dedicated trace connection. However, the amount of trace history provided by the MTB is limited by the size of SRAM allocated for trace operations.
Multi-ICE
A JTAG-based tool for debugging embedded systems.
Multi-layer interconnect
An interconnect scheme similar to a cross-bar switch. Each master on the interconnect has a direct link to each slave that is not shared with other masters. This means each master can process transfers in parallel with other masters. Contention in a multi-layer interconnect only occurs at a payload destination, typically a slave.
Multi-master AHB
Typically a shared, not multi-layer, AHB interconnect scheme. More than one master connects to a single AMBA AHB link. In this case, the bus is implemented with a set of full AMBA AHB master interfaces. Masters that use the AMBA AHB-Lite protocol must connect through a wrapper to supply full AMBA AHB master signals to support multi-master operation.
multithreading
In computer architecture, multithreading is the ability of a core in a multi-core processor to execute multiple processes or threads concurrently. Software threads are threads of execution managed by the operating system. One hardware thread can run many software threads.
MVA
The address produced by the FCSE that is sent to the rest of the memory system to be used in place of the normal virtual address. If the FCSE is absent or disabled, the MVA and the Virtual Address (VA) have the same value. From Armv6, Arm deprecates any use of the FCSE. The FCSE is optional in the unextended Armv7 architecture, and obsolete from the introduction of the Multiprocessing Extensions.
NaN
Not a number. In floating-point operation, NaNs are special floating-point values that can be used when neither a numeric value nor an infinity is appropriate. NaNs can be either:*Quiet NaNs that propagate through most floating-point operations.*Signaling NaNs that cause Invalid Operation floating-point exceptions.
Neon technology
The Arm technology that provides SIMD processing using a dedicated SIMD and floating-point register bank. Registers in this bank can be accessed as 128-bit registers, 64-bit registers, 32-bit registers, 16-bit registers, or 8-bit registers.
NEON technology
The ARM technology that provides SIMD processing using a dedicated SIMD and floating-point register bank. Registers in this bank can be accessed as 128-bit registers, 64-bit registers, 32-bit registers, 16-bit registers, or 8-bit registers.
Nested Vectored Interrupt Controller
The Nested Vectored Interrupt Controller (NVIC) facilitates low-latency exception and interrupt handling and controls power management. The Arm ARM provides more information on the NVIC registers.
nit
A unit of brightness equal to 1 cd.m-2, often used to measure display brightness.
noise reduction
Noise reduction describes either the removal or reduction of unwanted fluctuations in intensity from an imaging signal.
non-maskable interrupt
Non-secure Access Identifier
To differentiate between Protected and Non-Trusted entities, ARM defines 16 states that mark all processes within hardware and software. These states are defined using the Non-secure Access ID (NSAID), and each initiating device in the SoC has one or more NSAID values assigned in hardware. The NSAID enables other components to identify the initiating device for a particular transaction, and to identify whether the device is treated as Non-protected and therefore permitted to read data from other Non-protected masters.
non-tolerant
Non-tolerant is a feature in the I/O library.
Normal world
In software descriptions of the operation of an Arm core, effectively the environments that contain two virtual processors that run on a single core. The Secure world processes operations that are security-critical, and non security-critical operations are performed in the Normal world. Hardware descriptions use Secure state to describe a core that is executing in the Secure world, and Non-secure state to describe a core that is executing in the Normal world.
NR
Noise reduction describes either the removal or reduction of unwanted fluctuations in intensity from an imaging signal.
NSAID
To differentiate between Protected and Non-Trusted entities, ARM defines 16 states that mark all processes within hardware and software. These states are defined using the Non-secure Access ID (NSAID), and each initiating device in the SoC has one or more NSAID values assigned in hardware. The NSAID enables other components to identify the initiating device for a particular transaction, and to identify whether the device is treated as Non-protected and therefore permitted to read data from other Non-protected masters.
nSRST
Abbreviation of System Reset. The electronic signal that causes the target system other than the TAP controller to be reset. This signal is known as nSYSRST in some documentation.
nTRST
Abbreviation of TAP Reset. The electronic signal that causes the target system TAP controller to be reset. This signal is known as nICERST in some documentation.
NVIC
The Nested Vectored Interrupt Controller (NVIC) facilitates low-latency exception and interrupt handling and controls power management. The Arm ARM provides more information on the NVIC registers.
OFF
Short name for the Off power mode that can apply to the cores or the DSU.
OFF_EMU
Short name for the Emulated off power mode that can apply to the cores or the DSU.
Offline Compiler
A command-line tool that translates vertex shaders and fragment shaders written in the ESSL into binary vertex shaders and binary fragment shaders that you can link and run on the Mali GPU.
offset addressing
Addressing where the memory address is formed by adding an offset to, or subtracting an offset from, a base register value.
ON
Short name for the On power mode that can apply to the cores or the DSU.
on-target compiler
A component of the Mali GPU OpenGL ES 2.0 driver that translates shader source files provided by the graphics application, into binary shader code, at runtime.
OpenGL ES driver
Part of a driver stack that translates OpenGL ES API commands into data and instructions for the Mali GPU. Only the device driver controls the Mali GPU directly.
OpenGL ES Shading Language
A programming language this is used to create custom shader programs that can be used in a programmable pipeline, on the Mali GPU. You can also use pre-defined library shaders, which are written in ESSL.
OpenVG driver
Part of a driver stack that translates OpenVG API commands into data and instructions for the Mali GPU. Only the device driver controls the Mali GPU directly.
optical low pass filter
An optical low pass filter is a spatial filter which performs anti-aliasing, that is, it removes details which are too small for an image sensor to resolve.
OS-awareness
OS-awareness is a feature provided by RealView Debugger that enables you to:debug applications running on an embedded OS development platform, such as a Real-Time Operating System (RTOS) present thread information and scope some debugging operations to specific threads.
OTC
A power routing scheme, also referred to as ArtiGrid.
output section
A contiguous sequence of input sections that have the same RO, RW, or ZI attributes. The sections are grouped together in larger fragments called regions. The regions are grouped together into the final executable image.
Over The Cell
A power routing scheme, also referred to as ArtiGrid.
page-based hardware attributes
Page-based hardware attributes (PBHA) is an optional, implementation defined feature provided by cores. It allows software to set up to two bits in the translation tables, which are then propagated though the memory system with transactions, and can be used in the system to control system components.
PBHA
Page-based hardware attributes (PBHA) is an optional, implementation defined feature provided by cores. It allows software to set up to two bits in the translation tables, which are then propagated though the memory system with transactions, and can be used in the system to control system components.
PE
Abbreviation for processing element. Arm processor documentation usually describes a PE as a Core.
Performance Monitoring Unit
The Performance Monitoring Unit (PMU) enables software to get information about events that are taking place in the core and can be used for performance analysis and system debug.
PFT
The Program Flow Trace (PFT) architecture assumes that any trace decompressor has a copy of the program being traced, and generally outputs only enough trace for the decompressor to reconstruct the program flow. However, its trace output also enables a decompressor to reconstruct the program flow when it does not have a copy of parts of the program, for example because the program uses self-modifying code. A Program Flow Trace Macrocell(PTM) implements the Program Flow Trace architecture.
physical address
The physical address that identifies a location in physical memory.
PIL
A level of design hierarchy that includes and ARM processor and its immediate CoreSight components ready for integration into a CoreSight debug and trace system.
PISMO
Memory specification for plug-in memory modules.
pixel value
The pixel value is a single number that represents the brightness of the pixel. The most common pixel format is the byte image, where this number is stored as an 8-bit integer giving a range of possible values from 0 to 255. Typically zero is taken to be black, and 255 is taken to be white.
Platform Independent Storage Module
Memory specification for plug-in memory modules.
PLI
For Verilog simulators, an interface by which foreign code can be included in a simulation. Foreign code is code written in a different language.
PMM
In the context of graphics processors, a software routine that tracks the hardware blocks which can be enabled or disabled to reduce power. The PMM can control a specialized hardware unit, or a third-party power-management device, to power up or down each processor separately.
PMU
The Performance Monitoring Unit (PMU) enables software to get information about events that are taking place in the core and can be used for performance analysis and system debug.
POP
A performance optimization package for the implementation of an Arm processor using ARM Artisan optimized logic and memory physical IP
Power Management Module
In the context of graphics processors, a software routine that tracks the hardware blocks which can be enabled or disabled to reduce power. The PMM can control a specialized hardware unit, or a third-party power-management device, to power up or down each processor separately.
PPI
In the context of the GIC, this is a peripheral interrupt that is specific to a single processor.
PreCompiled Header
A header file that is precompiled. This avoids the compiler having to compile the file each time it is included by source files.
Prefetch Abort
An abort occurs when an illegal memory access causes an exception. An abort can be generated by the hardware that manages memory accesses, or by the external memory system. The hardware that generates the abort might be a Memory Management Unit (MMU) or a Memory Protection Unit (MPU).
prefetching
The process of fetching instructions from memory before the instructions that precede them have finished executing. Prefetching an instruction does not mean that the instruction must be executed.
Private Peripheral Interrupt
In the context of the GIC, this is a peripheral interrupt that is specific to a single processor.
Procedure Call Standard for the Arm Architecture
The Arm Architecture Procedure call Standard defines how registers and the stack are used for subroutine calls.
processing element
Abbreviated as PE. The abstract machine that is defined in the Arm architecture, as documented in an Arm Architecture Reference Manual. A processing element implementation that is compliant with the Arm architecture must conform with the behaviors that are described in the corresponding Arm Architecture Reference Manual.
Processor Integration Layer
A level of design hierarchy that includes and ARM processor and its immediate CoreSight components ready for integration into a CoreSight debug and trace system.
profiling
In the context of RealView Trace, the accumulation of statistics during execution of a program to measure performance or to determine critical areas of code.
Program Counter
The PC holds the virtual address of the next instruction to be executed, and: In AArch32 state, the PC is a 32-bit register, and is register R15 in the general-purpose register file. In AArch64 state, the PC is a 64-bit register, that is independent of the general-purpose registers X0-X30. In AArch64 state, software cannot write directly to the PC.
Program Flow Trace
The Program Flow Trace (PFT) architecture assumes that any trace decompressor has a copy of the program being traced, and generally outputs only enough trace for the decompressor to reconstruct the program flow. However, its trace output also enables a decompressor to reconstruct the program flow when it does not have a copy of parts of the program, for example because the program uses self-modifying code. A Program Flow Trace Macrocell(PTM) implements the Program Flow Trace architecture.
Program Status Register
Holds status and control information for a core, or for a program running on the core. When executing in AArch32 state, the Current Program Status Register (CPSR) is the active PSR that affects operation of the core. When executing in AArch64 state, PSTATE holds equivalent status information, but is not accessible as a single register. The Saved Program Status Register (SPSR) is a copy of the current state of the cores saved by the hardware on taking an exception. At the point where a core recognizes an exception: *If the exception is taken to AArch32 state, it copies the CPSR into the SPSR. *If the exception is taken to AArch64 state, it saves the current PSTATE to the SPSR.
Programming Language Interface
For Verilog simulators, an interface by which foreign code can be included in a simulation. Foreign code is code written in a different language.
protection region
A memory region whose position, size, and other properties are defined by the Memory Protection Unit registers.
Protection Unit
A hardware unit that controls a limited number of protection regions in memory. An MPU is the major component of an Arm Protected Memory System Architecture (PMSA).
PSR
Holds status and control information for a core, or for a program running on the core. When executing in AArch32 state, the Current Program Status Register (CPSR) is the active PSR that affects operation of the core. When executing in AArch64 state, PSTATE holds equivalent status information, but is not accessible as a single register. The Saved Program Status Register (SPSR) is a copy of the current state of the cores saved by the hardware on taking an exception. At the point where a core recognizes an exception: *If the exception is taken to AArch32 state, it copies the CPSR into the SPSR. *If the exception is taken to AArch64 state, it saves the current PSTATE to the SPSR.
PSTATE
In ARMv8, an abstraction of process state. All of the instruction sets include instructions that operate directly on elements of PSTATE. In previous versions of the architecture, the CPSR provides the equivalent functionality.
PU
A hardware unit that controls a limited number of protection regions in memory. An MPU is the major component of an Arm Protected Memory System Architecture (PMSA).
QoR
Quality of Results is a term used in evaluating technological processes.
QoS
Quality of Service
quadword
A 128-bit data item. Quadwords are normally at least word-aligned in Arm systems.
quadword-aligned
A data item having a memory address that is divisible by 16.
Quiet NaN
In floating-point arithmetic quiet NaNs, or qNaNs, do not raise any additional exceptions as they propagate through most operations. The exceptions are where the NaN cannot simply be passed through unchanged to the output, such as in format conversions or certain comparison operations, which do not expect a NaN input.
RAO
Hardware must implement the field as reading as all 1s. Software can rely on the field reading as all 1s. This description can apply to a single bit that reads as 1, or to a field that reads as all 1s.
RAO/SBOP
Read-As-One, Should-Be-One-or-Preserved on writes. Hardware must implement the field as Read-as-One, and must ignore writes to the field. Software can rely on the field reading as all 1s, but must use an SBOP policy to write to the field. This description can apply to a single bit that reads as 1, or to a field that reads as all 1s.
RAO/WI
Read-As-One, Writes Ignored. Hardware must implement the field as Read-as-One, and must ignore writes to the field. Software can rely on the field reading as all 1s, and on writes being ignored.This description can apply to a single bit that reads as 1, or to a field that reads as all 1s.
RAZ
Hardware must implement the field as reading as all 0s. Software can rely on the field reading as all 0s. This description can apply to a single bit that reads as 0, or to a field that reads as all 0s.
RAZ/SBZP
Read-As-Zero, Should-Be-Zero-or-Preserved on writes. Hardware must implement the field as Read-as-Zero, and must ignore writes to the field. Software can rely on the field reading as all 0s, but must use an SBZP policy to write to the field. This description can apply to a single bit that reads as 0, or to a field that reads as all 0s.
RAZ/WI
Read-As-Zero, Writes Ignored. Hardware must implement the field as Read-as-Zero, and must ignore writes to the field. Software can rely on the field reading as all 0s, and on writes being ignored. This description can apply to a single bit that reads as 0, or to a field that reads as all 0s.
RCbest
Refers to the corners that minimize the RC product.
RCT
On an Arm processor, a modification of the T32 instruction set to make it a better target for code generated at runtime. This is also called the T32 Execution Environment (T32EE). From Armv8, Arm processors do not support Jazelle RCT.
RCworst
Refers to the corners which maximize interconnect RC product.
RDDI
Remote Device Debug Interface (RDDI) is a C-level API which allows access to target debug and trace functionality, typically through a DSTREAM box, or a CADI model.
Read Write Position Independent
In the context of software executing on a core that implements the ARM architecture, read-write code or data that can be placed at any address.
read, modify, write
In a read, modify, write sequence, a value is read to a general-purpose register, the relevant fields updated in that register, and the new value written back.
Read-Allocate
Read-allocation is a technique that is used to deal with data store accesses to caches. In a Read-Allocate cache, the data is simply stored to main memory. Cache lines are only allocated to memory location when data is read or load
Read-As-One
Hardware must implement the field as reading as all 1s. Software can rely on the field reading as all 1s. This description can apply to a single bit that reads as 1, or to a field that reads as all 1s.
Read-As-Zero
Hardware must implement the field as reading as all 0s. Software can rely on the field reading as all 0s. This description can apply to a single bit that reads as 0, or to a field that reads as all 0s.
Read-Only Position Independent
In Arm compiler toolchains, a Read-Only Position Independent (ROPI) segment is often Position-Independent Code (PIC), but can be be read-only data, or a combination of PIC and read-only data. A program is Read-Only Position-Independent (ROPI) if all its read-only segments can be loaded to and used from any address in memory, without having to be recompiled. A read-only segment is often usually Position-Independent Code (PIC), but can be read-only data, or a combination of PIC and read-only data.
Read-Write Position Independent
In Arm compiler toolchains, a program is Read-Write Position-Independent (RWPI) if all its read-write segments can be loaded to, and used from, any address in memory, without needing recompiling. A read-write segment is usually Position-Independent Data (PID).
Real Time System Model
A software model of a development system, for example, the Emulation Baseboard. The model can run applications at almost full speed. This enables applications and operating systems to be written and debugged without a requirement for actual hardware.
RealMonitor
A small program that, when integrated into your target application or Real-Time Operating System (RTOS), enables you to observe and debug your target while parts of your application continue to run.
RealView Debugger
An ARM debugger that enables you to examine and control the execution of software running on a debug target. RealView Debugger is supplied as part of RVDS in both Windows and Red Hat Linux versions.
RealView Debugger Trace
Part of RVDS that extends the debugging capability with the addition of real-time program and data tracing. It is available from the RealView Debugger Code window.
RealView Development Suite
The RealView suite of software development tools, together with supporting documentation and examples, that enable you to write and debug applications for the Arm family of processors.
RealView ICE
An ARM JTAG interface unit for debugging embedded processor cores that uses a DBGTAP or Serial Wire interface.
RealView Instruction Set Simulator
One of the ARM simulators supplied with RVDS. RealView Instruction Set Simulator is a collection of programs that simulate the instruction sets and architecture of various ARM processors. This provides instruction-accurate simulation and enables ARM and Thumb executable programs to be run on non-native hardware. RVISS provides modules that model:*The ARM processor.*The memory used by the processor. There are alternative predefined models for each of these parts. However, you can create your own models if a supplied model does not meet your requirements.
RealView Trace and RealView Trace 2
Works in conjunction with RealView ICE to provide real-time trace functionality for software running in System-on-Chip devices with deeply embedded ARM processors. RealView Trace 2 also supports data streaming directly to ARM Profiler, providing real-time hardware platform profiling.
Redistributor
A Redistributor is a component of the GIC architecture. It is part of the interrupt routing infrastructure that is connected to the CPU interface, and thereby to the core.
region of interest
In the context of graphical display systems, a set of pixels in an image which will be treated differently from all others, by any filter or algorithm.
remapping
Changing the address of physical memory or devices after an application has started executing. This might be done to permit RAM to replace ROM when the initialization has completed.
replicator
In an ARM trace macrocell, enables two trace sinks to be wired together and to operate independently on the same incoming trace stream. The input trace stream is output onto two independent ATB ports.
RES0
A reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior. Used for fields in register descriptions. Also used for fields in architecturally defined data structures that are held in memory, for example in translation table descriptors. RES0 is not used in descriptions of instruction encodings. Within the architecture, there are some cases where a register bit or bitfield can be RES0 in some defined architectural context, but can have different defined behavior in a different architectural context. For any RES0 bit or field, software must not rely on the bit or field reading as 0, and must use an SBZP policy to write to the bit or field.
RES0H
A reserved bit or field with Should-Be-Zero-or-Preserved (SBZP). This behavior uses the Hardwired to 0 subset of the RES0 definition.
RES1
A reserved bit or field with Should-Be-One-or-Preserved (SBOP) behavior. Used for fields in register descriptions. Also used for fields in architecturally defined data structures that are held in memory, for example in translation table descriptors. RES1 is not used in descriptions of instruction encodings. Within the architecture, there are some cases where a register bit or bitfield can be RES1in some defined architectural context, but can have different defined behavior in a different architectural context. For any RES1 bit or bitfield, software must not rely on the bit or bitfield reading as 1, and must use an SBOP policy to write to the bit or bitfield.
RES1H
A reserved bit or field with Should-Be-Zero-or-Preserved (SBZP). This behavior uses the Hardwired to 1 subset of the RES1 definition.
Reserved
Unless otherwise stated in the architecture or product documentation: * Reserved instruction and 32-bit system control register encodings are UNPREDICTABLE. * Reserved 64-bit system control register encodings are undefined. * Reserved register bit fields are UNK/SBZP.
ROI
In the context of graphical display systems, a set of pixels in an image which will be treated differently from all others, by any filter or algorithm.
root region
In Arm compiler toolchains, a root region refers to an ELF region, which is an execution region in the image, where the address in the load view and in the execution view are the same. The initial entry point of an image and the vector table of a processor must be in a root region.
ROPI
In Arm compiler toolchains, a Read-Only Position Independent (ROPI) segment is often Position-Independent Code (PIC), but can be be read-only data, or a combination of PIC and read-only data. A program is Read-Only Position-Independent (ROPI) if all its read-only segments can be loaded to and used from any address in memory, without having to be recompiled. A read-only segment is often usually Position-Independent Code (PIC), but can be read-only data, or a combination of PIC and read-only data.
Round to Nearest
Input values are rounded to the nearest possible rounded value. Values exactly halfway between two possible rounded values will be rounded to the even value.
Round to Nearest with Ties to Away
All values will be rounded to the nearest number and selects the number with the larger magnitude if a tie occurs.
Round towards Minus Infinity
All values will be rounded down, regardless of which possible rounded value they are closer to.
Round towards Plus Infinity
All values will be rounded up, regardless of which possible rounded value they are closer to.
Round towards Zero
Positive values will be rounded down, and negative values rounded up, regardless of how close they are to the next possible rounded value.
rounding mode
In floating-point operation, specifies how the exact result of a floating-point operation is rounded to a value that is representable in the destination format. The IEEE 754 standard defines the required rounding modes for compliant floating-point implementations, and ARM implementations support these rounding modes. Note The IEEE 754-2008 standard changes the term Rounding mode to Rounding-direction attribute. ARM documentation continues to use the term Rounding mode, as defined in the IEEE 754-1985 standard.
RSD
In the context of software executing on a core that implements the ARM architecture, Read-Only Position Independent describes code or read-only data that can be placed at any address.
RTL
Register Description Language.
RTSM
A software model of a development system, for example, the Emulation Baseboard. The model can run applications at almost full speed. This enables applications and operating systems to be written and debugged without a requirement for actual hardware.
Running System Debug
In the context of software executing on a core that implements the ARM architecture, Read-Only Position Independent describes code or read-only data that can be placed at any address.
RVCT
A suite of tools that, together with supporting documentation and examples, enables you to write and build applications for ARM processors.
RVDS
The RealView suite of software development tools, together with supporting documentation and examples, that enable you to write and debug applications for the Arm family of processors.
RVI
An ARM JTAG interface unit for debugging embedded processor cores that uses a DBGTAP or Serial Wire interface.
RVISS
One of the ARM simulators supplied with RVDS. RealView Instruction Set Simulator is a collection of programs that simulate the instruction sets and architecture of various ARM processors. This provides instruction-accurate simulation and enables ARM and Thumb executable programs to be run on non-native hardware. RVISS provides modules that model:*The ARM processor.*The memory used by the processor. There are alternative predefined models for each of these parts. However, you can create your own models if a supplied model does not meet your requirements.
RWPI
In the context of software executing on a core that implements the ARM architecture, read-write code or data that can be placed at any address.
Saved Program Status Register
A register used to save the state of the core on taking an exception.
SBO
Hardware must ignore writes to the field. Software should write the field as all 1s. If software writes a value that is not all 1s, it must expect an UNPREDICTABLE result. This description can apply to a single bit that should be written as 1, or to a field that should be written as all 1s.
SBOP
The ARMv7 Large Physical Address Extension modified the definition of SBOP to apply to register fields that are SBOP in some but not all contexts. From the introduction of ARMv8 such register fields are described as RES1. The definition of SBOP given here applies only to fields that are SBOP in all contexts. Hardware must ignore writes to the field. When writing this field, software must either write all 1s to this field, or, if the register is being restored from a previously read state, this field must be written with the previously read value. If this is not done, then the result is UNPREDICTABLE. This description can apply to a single bit that should be written as its preserved value or as 1, or to a field that should be written as its preserved value or as all 1s.
SBZ
Hardware must ignore writes to the field. Software should write the field as all 0s. If software writes a value that is not all 0s, it must expect an UNPREDICTABLE result. This description can apply to a single bit that should be written as 0, or to a field that should be written as all 0s.
SBZP
The Large Physical Address Extension modifies the definition of SBZP for register bits that are reallocated by the extension, and as a result are SBZP in some but not all contexts. The generic definition of SBZP given here applies only to bits that are not affected by this modification. Hardware must ignore writes to the field. When writing this field, software must either write all 1s to this field, or, if the register is being restored from a previously read state, this field must be written previously read value. If this is not done, then the result is UNPREDICTABLE. This description can apply to a single bit that should be written as its preserved value or as 0, or to a field that should be written as its preserved value or as all 0s.
scatter-loading
Assigning the address and grouping of code and data sections individually rather than using single large blocks.
SCC
On CoreTile Express daughterboards, a register interface in the test chip or development chip on the daughterboard, that the Versatile Express configuration system uses to configure the chip. On LogicTile Express daughterboards, a register interface in the FPGA on the daughterboard, that the Versatile Express configuration system uses to configure the FPGA. The configuration system loads values into the registers at powerup or reset and during runtime.
SDF
A file format that contains timing information to the level of individual bits of buses and is used in SDF back-annotation. An SDF file can be generated in a number of ways, but most commonly from a delay calculator.
section
In Arm Compiler toolchains, a section refers to an ELF file section, which is the smallest unit of code and data on which a linker can operate.
Secure Attribution Unit
The Arm®v8‑M architecture defines a mechanism whereby an implementation can define whether any particular address is exempt from checking, is NSC or Secure. If the ARMv8‑M Security Extension is included, then the internal Security Attribution Unit (SAU) or an external Implementation Defined Attribution Unit (IDAU) determines the Security state attributed to each address.
Secure world
In software descriptions of the operation of an Arm core, effectively the environments that contain two virtual processors that run on a single core. The Secure world processes operations that are security-critical, and non security-critical operations are performed in the Normal world. Hardware descriptions use Secure state to describe a core that is executing in the Secure world, and Non-secure state to describe a core that is executing in the Non-secure state.
Security Attribution Unit
The Arm®v8‑M architecture defines a mechanism whereby an implementation can define whether any particular address is exempt from checking, is NSC or Secure. If the ARMv8‑M Security Extension is included, then the internal Security Attribution Unit (SAU) or an external Implementation Defined Attribution Unit (IDAU) determines the Security state attributed to each address.
semihosting
A mechanism to communicate Input/Output (I/O) requests from application code to a host workstation running a debugger. For example, you can use semihosting to enable functions in the C library, such as printf() and scanf(), to use the screen and keyboard on the host workstation instead of having a screen and keyboard on the target system.
SEooC
Abbreviation for Safety Element out of Context.
Serial Configuration Controller
On CoreTile Express daughterboards, a register interface in the test chip or development chip on the daughterboard, that the Versatile Express configuration system uses to configure the chip. On LogicTile Express daughterboards, a register interface in the FPGA on the daughterboard, that the Versatile Express configuration system uses to configure the FPGA. The configuration system loads values into the registers at powerup or reset and during runtime.
Serial Power Controller
On Versatile Express CoreTile daughterboards, a register interface in an ARM test chip or development chip that the Versatile Express configuration system uses to configure the power controller within the chip. The SPC registers define the power status, supply levels and clock values of the internal power domains within the chip.
Serial Wire Debug
A debug implementation that uses a serial connection between the SoC and a debugger. This connection normally requires a bidirectional data signal and a separate clock signal, rather than the four to six signals required for a JTAG connection.
Serial Wire Debug Port
The Serial Wire Debug Port(SW-DP) is the interface for Serial Wire Debug.
Shared layer
In general, contains functions used by more than one Mali GPU driver. It contains math functions, texture processing and list utilities.
Shared Peripheral Interrupt
In the context of an Arm GIC, this is a peripheral interrupt that the Distributor can route to any of a specified combination of processors. Each peripheral interrupt is either: *Edge-triggered This is an interrupt that is asserted on detection of a rising edge of an interrupt signal and then, regardless of the state of the signal, remains asserted until it is cleared by the conditions defined by this specification. *Level-sensitive This is an interrupt that is asserted whenever the interrupt signal level is active, and deasserted whenever the level is not active.
Should-Be-One
Hardware must ignore writes to the field. Software should write the field as all 1s. If software writes a value that is not all 1s, it must expect an UNPREDICTABLE result. This description can apply to a single bit that should be written as 1, or to a field that should be written as all 1s.
Should-Be-One-or-Preserved
The ARMv7 Large Physical Address Extension modified the definition of SBOP to apply to register fields that are SBOP in some but not all contexts. From the introduction of ARMv8 such register fields are described as RES1. The definition of SBOP given here applies only to fields that are SBOP in all contexts. Hardware must ignore writes to the field. When writing this field, software must either write all 1s to this field, or, if the register is being restored from a previously read state, this field must be written with the previously read value. If this is not done, then the result is UNPREDICTABLE. This description can apply to a single bit that should be written as its preserved value or as 1, or to a field that should be written as its preserved value or as all 1s.
Should-Be-Zero
Hardware must ignore writes to the field. Software should write the field as all 0s. If software writes a value that is not all 0s, it must expect an UNPREDICTABLE result. This description can apply to a single bit that should be written as 0, or to a field that should be written as all 0s.
Should-Be-Zero-or-Preserved
The Large Physical Address Extension modifies the definition of SBZP for register bits that are reallocated by the extension, and as a result are SBZP in some but not all contexts. The generic definition of SBZP given here applies only to bits that are not affected by this modification. Hardware must ignore writes to the field. When writing this field, software must either write all 1s to this field, or, if the register is being restored from a previously read state, this field must be written previously read value. If this is not done, then the result is UNPREDICTABLE. This description can apply to a single bit that should be written as its preserved value or as 0, or to a field that should be written as its preserved value or as all 0s.
signaling NaN
In floating-point operation, the floating-point hardware causes an Invalid Operation exception whenever any floating-point operation receives a signaling NaN as an operand. You can use signaling NaNs in debugging, to track down some uses of uninitialized variables.
Sign-Off Model
A Sign-Off-Model (SOM) is an opaque, compiled simulation model generated from a technology-specific netlist of an Arm processor, derived after gate level synthesis and timing annotation, that you can use in back-annotated gate-level simulations to prove the function and timing behavior of the device. A SOM provides accurate timing simulation of an SoC, and supports simulation using production test vectors from the Automatic Test Pattern Generation (ATPG) tool. It only supports back-annotation using SDF files. The SOM includes timing information but provides slower simulation than a DSM.
SIMD
In the ARM instruction sets, supported SIMD instructions can comprise: *Instructions that perform parallel operations on the bytes or halfwords of the ARM core registers. *Instructions that perform vector operations. That is, they perform parallel operations on vectors held in multiword registers. Different versions of the ARM architecture support and recommend different instructions for vector operations.
simple sequential execution
The behavior of an implementation that fetches, decodes, and completely executes each instruction before proceeding to the next instruction. Such an implementation performs no speculative accesses to memory, including to instruction memory. The implementation does not pipeline any phase of execution. In practice, this is the theoretical execution model that the architecture is based on, and ARM does not expect this model to correspond to a realistic implementation of the architecture.
simple tracepoint
A type of tracepoint that enables you to set trigger points, trace start and end points, or trace ranges for memory and data accesses.
Single Instruction, Multiple Data
In the ARM instruction sets, supported SIMD instructions can comprise: *Instructions that perform parallel operations on the bytes or halfwords of the ARM core registers. *Instructions that perform vector operations. That is, they perform parallel operations on vectors held in multiword registers. Different versions of the ARM architecture support and recommend different instructions for vector operations.
SMMU
A System MMU is a hardware device designed to provide address translation services and protection functionalities to any DMA capable agent in the system other than the main processor. This includes hardware accelerators such as GPUs and Video Engines (VEs), simple DMA controllers as well as complete sub-systems. The SMMU can be implemented as a standalone device or integrated with an existing DMA capable processing unit.
SoC
Abbreviation for System on Chip. A complete system (e.g. mobile phone, set-top box, etc.) on a single device.
software breakpoint
A breakpoint that is implemented by replacing an instruction in memory with one that causes the processor to take an exception. Because instruction memory must be altered, software breakpoints cannot be used where instructions are stored in read-only memory.
Software Test Library
A Software Test Library (STL) is used when testing the functional safety of Arm-based cores to detect failures in functional logic (excluding memory), such as during the startup and run time of the core.
SOM
A Sign-Off-Model (SOM) is an opaque, compiled simulation model generated from a technology-specific netlist of an Arm processor, derived after gate level synthesis and timing annotation, that you can use in back-annotated gate-level simulations to prove the function and timing behavior of the device. A SOM provides accurate timing simulation of an SoC, and supports simulation using production test vectors from the Automatic Test Pattern Generation (ATPG) tool. It only supports back-annotation using SDF files. The SOM includes timing information but provides slower simulation than a DSM.
SP
On ARM cores, SP refers to the stack pointer for the hardware-managed stack, and: In AArch32 state, the SP is register R13 in the general-purpose register file. In AArch64 state, there is a dedicated SP for each implemented Exception level.
SPC
On Versatile Express CoreTile daughterboards, a register interface in an ARM test chip or development chip that the Versatile Express configuration system uses to configure the power controller within the chip. The SPC registers define the power status, supply levels and clock values of the internal power domains within the chip.
Speculative
SPI
In the context of an Arm GIC, this is a peripheral interrupt that the Distributor can route to any of a specified combination of processors. Each peripheral interrupt is either: *Edge-triggered This is an interrupt that is asserted on detection of a rising edge of an interrupt signal and then, regardless of the state of the signal, remains asserted until it is cleared by the conditions defined by this specification. *Level-sensitive This is an interrupt that is asserted whenever the interrupt signal level is active, and deasserted whenever the level is not active.
SPI
The Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift registers, sensors, and SD cards.
SPICE
Simulation Program with Integrated Circuit Emphasis. An accurate transistor-level electronic circuit simulation tool that can predict how an equivalent real circuit behaves for given circuit conditions.
SPSR
A register used to save the state of the core on taking an exception.
stack pointer
On ARM cores, SP refers to the stack pointer for the hardware-managed stack, and: In AArch32 state, the SP is register R13 in the general-purpose register file. In AArch64 state, there is a dedicated SP for each implemented Exception level.
Standard Delay Format
A file format that contains timing information to the level of individual bits of buses and is used in SDF back-annotation. An SDF file can be generated in a number of ways, but most commonly from a delay calculator.
STL
A Software Test Library (STL) is used when testing the functional safety of Arm-based cores to detect failures in functional logic (excluding memory), such as during the startup and run time of the core.
STM
System Trace Macrocell - A trace source designed primarily for high-bandwidth trace of instrumentation embedded into software. This instrumentation is made up of memory-mapped writes to the STM, which carry information about the behavior of the software.
Strongly-ordered memory
Memory regions with the strongest ordering requirement. From the introduction of ARMv8, these regions are described as Device-nGnRnE, indicating that the region is: * non-Gathering - Multiple memory accesses must not be merged into a single access. * non-Reordering - Multiple memory accesses must not be reordered. * no Early Write Acknowledge - A hint to the memory system that only the endpoint of a write access should return an acknowledge for that write access.
subnormal value
The IEEE 754-2008 standard term for a floating-point operand with a zero exponent and a nonzero fraction field. Arm documentation describes these operands as denormal or denormalized, as defined by the IEEE 754-1985 standard.
Supervisor Call
An instruction that causes the processor to take a Supervisor Call exception. Used by the ARM standard C library to handle semihosting.
support code
In a floating-point implementation that requires a floating-point subarchitecture, system software that complements the hardware floating-point implementation. The support code can provide a library of routines that perform operations beyond the scope of the hardware, and can include a set of exception handlers to process exceptional conditions in compliance with the IEEE 754 standard.
SVC
An instruction that causes the processor to take a Supervisor Call exception. Used by the ARM standard C library to handle semihosting.
SWD
A debug implementation that uses a serial connection between the SoC and a debugger. This connection normally requires a bidirectional data signal and a separate clock signal, rather than the four to six signals required for a JTAG connection.
SW-DP
The Serial Wire Debug Port(SW-DP) is the interface for Serial Wire Debug.
SWI
An instruction that causes the processor to take a Supervisor Call exception. Used by the ARM standard C library to handle semihosting.
SWJ - DP
The SWJ-DP is a combined JTAG-DP and SW-DP that you can use to connect either a Serial Wire Debug (SWD) or JTAG probe to a target.
synchronization primitive
An instruction that is used to ensure memory synchronization, for example LDREX or STREX.
System Control Space
On Cortex-M series processors, a memory-mapped region from 0xE000E000 to 0xE000EFFF that provides system control and configuration registers, including control of the Nested Vectored Interrupt Controller (NVIC) and debug functions.
System on Chip
A complete system (e.g. mobile phone, set-top box, etc.) on a single device.
System Trace Macrocell
System Trace Macrocell - A trace source designed primarily for high-bandwidth trace of instrumentation embedded into software. This instrumentation is made up of memory-mapped writes to the STM, which carry information about the behavior of the software.
T32
An instruction set that can be used by an ARMv8 processor that is in AArch32 execution state. T32 is a variable-length instruction set that uses both 16-bit and 32-bit instruction encodings. It is compatible with the ARMv7 Thumb instruction set.
T32 instruction
An instruction that can be used by a core that is in AArch32 execution state. T32(Thumb) is a variable-length instruction set that uses both 16-bit and 32-bit instruction encodings. It is the only instruction set supported by ARM M-profile processors.
T32 state
When a core is executing in AArch32 state, if it is in T32(Thumb) Instruction set state then it executes T32 instructions.
T32EE instruction
One or two halfwords that specify an operation to perform for a core that is in AArch32 state and in T32EE(ThumbEE) Instruction set state.
T32EE state
In AArch32 state, in the T32EE (ThumbEE) Instruction set state the core executes the T32EE instruction set.
TAP
The collection of four mandatory and one optional terminals that form the input/output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. In the JTAG standard, the nTRST signal is optional, but this signal is mandatory in ARM processors because it is used to reset the debug logic.
TAP Controller
Logic on a device that enables access to some or all of that device for test purposes. The circuit functionality is defined in IEEE1149.1.
TCD
A generic term to describe Trace Port Analyzers, logic analyzers, and on-chip trace buffers.
TCK
The electronic clock signal that times data on the TAP data lines TMS, TDI, and TDO.
TCM
An area of low latency memory that provides predictable instruction execution or data load timing, for cases where deterministic performance is required. TCMs are suited to holding: *Critical routines such as for interrupt handling. *Scratchpad data. *Data types whose locality is not suited to caching. *Critical data structures, such as interrupt stacks.
TDI
Test Data Input (TDI) is the electronic signal input to a TAP controller from the data source (upstream). Usually this is seen connecting the RealView ICE run control unit to the first TAP controller.
TDO
Test Data Output (TDO) is the electronic signal output from a TAP controller to the downstream data sink. Usually this connects the last TAP controller to the RealView ICE run control unit.
Test Access Port
The collection of four mandatory and one optional terminals that form the input/output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. In the JTAG standard, the nTRST signal is optional, but this signal is mandatory in ARM processors because it is used to reset the debug logic.
Test Data Input
Test Data Input (TDI) is the electronic signal input to a TAP controller from the data source (upstream). Usually this is seen connecting the RealView ICE run control unit to the first TAP controller.
Test Data Output
Test Data Output (TDO) is the electronic signal output from a TAP controller to the downstream data sink. Usually this connects the last TAP controller to the RealView ICE run control unit.
Texture Descriptor
Data structure used by the Mali GPU to describe one texture map.
Thin Links
A protocol to reduce the number of signals in an AXI point-to-point connection to simplify routing.
Thumb instruction
An instruction that can be used by a core that is in AArch32 execution state. T32(Thumb) is a variable-length instruction set that uses both 16-bit and 32-bit instruction encodings. It is the only instruction set supported by ARM M-profile processors.
Thumb instruction set
An instruction set that can be used by a core that is in AArch32 execution state. It is the only instruction set supported by ARM M-profile processors.
Thumb state
When a core is executing in AArch32 state, if it is in T32(Thumb) Instruction set state then it executes T32 instructions.
Thumb-2
The technology, introduced in ARMv6T2, that extends the Thumb instruction set to a variable-length instructions set that includes both 16-bit and 32-bit instructions.
ThumbEE instruction
One or two halfwords that specify an operation to perform for a core that is in AArch32 state and in T32EE(ThumbEE) Instruction set state.
ThumbEE state
In AArch32 state, in the T32EE (ThumbEE) Instruction set state the core executes the T32EE instruction set.
Tightly Coupled Memory
An area of low latency memory that provides predictable instruction execution or data load timing, for cases where deterministic performance is required. TCMs are suited to holding: *Critical routines such as for interrupt handling. *Scratchpad data. *Data types whose locality is not suited to caching. *Critical data structures, such as interrupt stacks.
tile buffer
A memory buffer inside the Mail GPU that holds the framebuffer contents for the tile that is currently being rendered. The tile buffer can be accessed without using the memory bus.
TLB
A memory structure containing the results of translation table walks. TLBs help to reduce the average cost of memory accesses.
TLB lockdown
Prevents specific translation table walk results being removed from the TLB.
TLX
A protocol to reduce the number of signals in an AXI point-to-point connection to simplify routing.
TMC
Controls the capturing or buffering trace generated by trace sources within a system. The TMC receives trace from an ATB interface and can be configured to perform one of the following: * Route the trace out over an AXI master interface, to allow trace to be captured in system memory or in other peripherals. * Capture the trace in a circular buffer in dedicated SRAM. * Buffer the trace in a First In First Out (FIFO) style, to smooth over peaks in trace bandwidth.
TMS
Test Mode Select.
TPA
A hardware device that captures trace information that is output on a trace port.
TPIU
Drains trace data and acts as a bridge between the on-chip trace data and the data stream captured by a Trace Port Analyzer.
Trace Capture Device
A generic term to describe Trace Port Analyzers, logic analyzers, and on-chip trace buffers.
trace driver
A remote debug interface target that controls a piece of trace hardware. That is, the trigger macrocell, trace macrocell, and trace capture tool.
trace funnel
In an ARM trace macrocell, a device that combines multiple trace sources onto a single bus.
trace hardware
A device that contains an ARM trace macrocell.
Trace Memory Controller
Controls the capturing or buffering trace generated by trace sources within a system. The TMC receives trace from an ATB interface and can be configured to perform one of the following: * Route the trace out over an AXI master interface, to allow trace to be captured in system memory or in other peripherals. * Capture the trace in a circular buffer in dedicated SRAM. * Buffer the trace in a First In First Out (FIFO) style, to smooth over peaks in trace bandwidth.
trace port
A port on a device, such as a processor or ASIC, used to output trace information.
Trace Port Analyzer
A hardware device that captures trace information that is output on a trace port.
Trace Port Interface Unit
Drains trace data and acts as a bridge between the on-chip trace data and the data stream captured by a Trace Port Analyzer.
Tracepoint unit
In the context of an ARM debugger, a unit within a Chained tracepoint that combines with other tracepoint units to create a complex tracepoint.
Translation Lookaside Buffer
A memory structure containing the results of translation table walks. TLBs help to reduce the average cost of memory accesses.
translation table
A table, held in memory, that contains descriptors that define the mapping between a supplied input address and the corresponding output address, and the properties of the memory region at that address. In an ARM system without support for virtualization, the input address is a physical address and the output address is a virtual address. In the ARM processor architecture, a page table is called a translation table, and a page table walk is called a translation table walk.
translation table walk
A full translation table lookup. It is performed automatically by hardware.
trap enable bits
For floating-point operation, the trap enable bits determine whether trapped or untrapped exception handling is selected. If trapped exception handling is selected, the way it is carried out is IMPLEMENTATION DEFINED.
triangle setup unit
A component of a fragment processor. The triangle setup unit prepares primitives for rendering by calculating the data required to rasterize and shade the primitive.
trigger
In the context of tracing, a trigger is an event that instructs the debugger to stop collecting trace and display the trace information around the trigger position, without halting the core. The exact information that is displayed depends on the position of the trigger within the buffer.
trigger instruction
In a floating-point implementation that requires a floating-point subarchitecture, a trigger instruction is a floating-point instruction that causes a bounce when it is issued.
Trigger Interface
Part of an Embedded Cross Trigger (ECT) device. In an ECT, the CTI provides the interface between a processor or ETM and the CTM.
TRM
Abbreviation for Technical Reference Manual
TrustZone Software
A secure software framework that uses the ARM architecture Security Extensions.
TrustZone technology
The hardware and software that enable the integration of enhanced security features throughout an SoC. In Armv6K, Arm7-A and Armv8-M, the Security Extensions implement the TrustZone hardware. In Armv8, EL3 incorporates the TrustZone hardware.
UAL
Unified Assembler Language (UAL) is a common assembly language syntax for both A32 and T32 instructions. Code written using UAL can be built for both A32 and T32 state. UAL syntax can be used with both armasm and armclang integrated assembler.
UMP
Unified Memory Provider. Provides a safe way to share memory across processes, drivers and hardware components, possibly using an MMU or MPU for memory protection. The Mali GPU driver stack uses the UMP API for certain optional functionality.
unconditional breakpoint
In the context of an ARM debugger, a breakpoint that does not have a conditional qualifier assigned. The breakpoint activates immediately when it is hit, but subsequent image execution is determined by any actions assigned to the breakpoint.
UNDEFINED
Indicates an instruction that is not architecturally defined. It generates an UNDEFINED Instruction exception.
Unified Assembler Language
Unified Assembler Language (UAL) is a common assembly language syntax for both A32 and T32 instructions. Code written using UAL can be built for both A32 and T32 state. UAL syntax can be used with both armasm and armclang integrated assembler.
Unified Memory Provider
Unified Memory Provider. Provides a safe way to share memory across processes, drivers and hardware components, possibly using an MMU or MPU for memory protection. The Mali GPU driver stack uses the UMP API for certain optional functionality.
UNK
An abbreviation indicating that software must treat a field as containing an UNKNOWN value. In any implementation, the bit must read as 0, or all 0s for a bit field. Software must not rely on the field reading as zero.
UNK/SBOP
Hardware must implement the field as Read-As-One, and must ignore writes to the field. Software must not rely on the field reading as all 1s, and except for writing back to the register it must treat the value as if it is UNKNOWN. Software must use an SBOP policy to write to the field. This description can apply to a single bit that should be written as its preserved value or as 1, or to a field that should be written as its preserved value or as all 1s.
UNK/SBZP
Hardware must implement the field as Read-As-Zero, and must ignore writes to the field. Software must not rely on the field reading as all 0s, and except for writing back to the register it must treat the value as if it is unknown. Software must use an SBZP policy to write to the field. This description can apply to a single bit that should be written as its preserved value or as 0, or to a field that should be written as its preserved value or as all 0s.
UNKNOWN
An UNKNOWN value does not contain valid data, and can vary from moment to moment, instruction to instruction, and implementation to implementation. An UNKNOWN value must not return information that cannot be accessed at the current or a lower level of privilege using functionality that are not UNPREDICTABLE or CONSTRAINED UNPREDICTABLE and do not return UNKNOWN values. An UNKNOWN value must not be documented or promoted as having a defined value or effect. When UNKNOWN appears in body text, it is always in small capitals.
UNP
For an ARM processor, UNPREDICTABLE means the behavior cannot be relied upon. UNPREDICTABLE behavior must not perform any function that cannot be performed at the current or a lower level of privilege using instructions that are not UNPREDICTABLE. UNPREDICTABLE behavior must not be documented or promoted as having a defined effect. An instruction that is UNPREDICTABLE can be implemented as UNDEFINED. In an implementation that supports Virtualization, the Non-secure execution of UNPREDICTABLE instructions at a lower level of privilege can be trapped to the hypervisor, provided that at least one instruction that is not UNPREDICTABLE can be trapped to the hypervisor if executed at that lower level of privilege. For an ARM trace macrocell, UNPREDICTABLE means that the behavior of the macrocell cannot be relied on. Such conditions have not been validated. When applied to the programming of an event resource, only the output of that event resource is UNPREDICTABLE. UNPREDICTABLE behavior can affect the behavior of the entire system, because the trace macrocell can cause the core to enter debug state, and external outputs can be used for other purposes.
UNPREDICTABLE
For an ARM processor, UNPREDICTABLE means the behavior cannot be relied upon. UNPREDICTABLE behavior must not perform any function that cannot be performed at the current or a lower level of privilege using instructions that are not UNPREDICTABLE. UNPREDICTABLE behavior must not be documented or promoted as having a defined effect. An instruction that is UNPREDICTABLE can be implemented as UNDEFINED. In an implementation that supports Virtualization, the Non-secure execution of UNPREDICTABLE instructions at a lower level of privilege can be trapped to the hypervisor, provided that at least one instruction that is not UNPREDICTABLE can be trapped to the hypervisor if executed at that lower level of privilege. For an ARM trace macrocell, UNPREDICTABLE means that the behavior of the macrocell cannot be relied on. Such conditions have not been validated. When applied to the programming of an event resource, only the output of that event resource is UNPREDICTABLE. UNPREDICTABLE behavior can affect the behavior of the entire system, because the trace macrocell can cause the core to enter debug state, and external outputs can be used for other purposes.
user space gator
An agent installed on a Streamline Performance Analyzer target.
VA
Virtual Address. An address used in an instruction as a data or instruction address. The PC, LR, and SP always hold virtual addresses. For a Protected Memory System Architecture (PMSA) implementation, the virtual address is identical to the physical address.
VBI
On a display panel, the vertical blanking interval is the period of time after the final pixel of an image has been updated, and before the first pixel of the next image is updated.
VDMA
Video Direct Memory Access. VDMA transfers data in a burst-efficient way to and from system memory.
vectorization
Vectorization is a type of optimization where a compiler converts a sequence of operations into vector operations that perform SIMD processing.
veneer
In Arm compiler toolchains, veneers are small sections of code generated by the linker and inserted into a program. A linker might generate veneers when a branch involves a destination beyond the branching range.
vertex
The data set that defines the properties of one point of a primitive. For example, a point primitive, an endpoint of a line primitive, or a corner of a triangle primitive.
vertex attributes
The data that is provided by the application to define a vertex.
vertex loader
A component of the vertex processor that loads vertex attributes from memory into the vertex shader unit.
vertex processor
A programmable processor that executes vertex shaders with typical transform and lightning calculations, and generates lists of primitives for a fragment processor to draw.
vertex shader
A program running on a vertex processor or shader core that calculates the position and other characteristics, such as color and texture coordinates, for each vertex.
vertex shader unit
A programmable component of the vertex processor that runs vertex shaders.
Vertical Blanking Interval
On a display panel, the vertical blanking interval is the period of time after the final pixel of an image has been updated, and before the first pixel of the next image is updated.
VFP
The original name of the extension to the ARM architecture that provided floating-point arithmetic. From ARMv8-A, the architecture includes support for floating-point instructions, rather than this being an architecture extension.
VFP Support Code
Vector Floating-Point (VFP) support code is code provided to handle cases that VFP hardware is unable to process.
VIA
victim
A cache line selected to be discarded to make room for a replacement cache line. This is required because of a cache miss. How it is selected for eviction is processor-specific.
virtual address
Virtual Address. An address used in an instruction as a data or instruction address. The PC, LR, and SP always hold virtual addresses. For a Protected Memory System Architecture (PMSA) implementation, the virtual address is identical to the physical address.
Virtual Machine Identifier
Some Translation Lookaside Buffers (TLBs) store Virtual Machine Identifiers (VMIDs) in each TLB entry. Each guest operating system is assigned a unique Virtual Machine Identifier (VMID) by the hypervisor. The VMID allows the core to move from one virtual machine to another (also known as a virtual machine switch switch) without having to invalidate TLB entries.
Virtual Memory System Architecture
A Virtual Memory System Architecture (VMSA) defines and describes how virtual addresses are translated into physical addresses, including the attributes and permissions that can be assigned to the addresses. In a processing element, the Memory Management Unit (MMU) performs this address translation and enforces these permissions.
VMID
Some Translation Lookaside Buffers (TLBs) store Virtual Machine Identifiers (VMIDs) in each TLB entry. Each guest operating system is assigned a unique Virtual Machine Identifier (VMID) by the hypervisor. The VMID allows the core to move from one virtual machine to another (also known as a virtual machine switch switch) without having to invalidate TLB entries.
VMSA
A Virtual Memory System Architecture (VMSA) defines and describes how virtual addresses are translated into physical addresses, including the attributes and permissions that can be assigned to the addresses. In a processing element, the Memory Management Unit (MMU) performs this address translation and enforces these permissions.
von Neumann
The von Neumann computer architecture stores data and programs together in memory. This architecture differs from the Harvard computer architecture where data and instructions are stored in separate memory areas.
Vt
Threshold voltage
Wakeup Interrupt Controller
The Wakeup Interrupt Controller (WIC) is a peripheral that can detect an interrupt and wake the processor from deep sleep mode. The WIC is enabled only when the system is in deep sleep mode.
Warm reset
A reset that initializes most of the processor functionality, excluding the debug controller and debug logic.
watchpoint
A debug event triggered by an access to memory, specified in terms of the address of the location in memory being accessed.
WB
White balance refers to the global adjustment of color channels in an image.
White Point
The definition of neutral tones in an image, color space, or display. It might be a color space coordinate or a ratio between color channel values.
word-aligned
Having a memory address that is divisible by four.
word-invariant
In a word-invariant system, the address of each byte of memory changes when switching between little-endian and big-endian operation, in such a way that the byte with address A in one endianness has address A EOR 3 in the other endianness. As a result, each aligned word of memory always consists of the same four bytes of memory in the same order, regardless of endianness. The change of endianness occurs because of the change to the byte addresses, not because the bytes are rearranged. The ARM architecture supports word-invariant systems in ARMv3 and later versions. When word-invariant support is selected, the behavior of load or store instructions with unaligned addresses is instruction-specific, and is in general not the expected behavior for an unaligned access. ARM strongly recommends that word-invariant systems use the endianness that produces the required byte addresses at all times, possibly apart from very early in their reset handlers before they have set up the endianness, and that this early part of the reset handler uses only word-aligned memory accesses.
WP
The definition of neutral tones in an image, color space, or display. It might be a color space coordinate or a ratio between color channel values.
write completion
The memory system indicates to the core that a write is complete at a point in the transaction where the memory system can guarantee that the write is observable by all processors in the system. An additional recommendation for Device-nGnRnE memory (Strongly-ordered memory), is that a write to a memory-mapped peripheral is complete only when it reaches that memory-mapped peripheral and therefore can trigger any side effects caused by the memory-mapped peripheral. Write completion is not required to ensure that all side effects are globally visible, although some peripherals might define this as a required property of completed writes.
write interleave capability
For an interface to an interconnect, the number of data-active write transactions for which the interface can transmit data. This is counted from the earliest transaction.
write interleave depth
The number of data-active write transactions for which the interface can receive data.
Write-Access
Write-Access can be configured for to enable writes to areas of memory or particular registers.
Write-Allocate
A data storage method in which, if a memory location to be written is not in cache memory, a cache line is allocated for the memory. The value of that memory is then loaded into the cache from main memory, and the new value for the location is written to cache.
Write-Back
A data storage method in which a write updates the cache only and marks the cache line as dirty. External memory is updated only when the line is evicted or explicitly cleaned.
write-back
Writing back a modified value to the base register used in an address calculation.
Write-Through
A data storage method in which data is written into the cache and the corresponding main memory location at the same time.
XTSM
The XVC Test Scenario Manager is a component that coordinates the operation of multiple XVCs.
XVC
Extensible Verification Component. A model that provides system or device stimulus and monitor responses.
XVC Test Scenario Manager
The XVC Test Scenario Manager is a component that coordinates the operation of multiple XVCs.
YcbCr
One of two primary color spaces used to represent digital component video (the other is RGB). The difference between YCbCr and RGB is that YCbCr represents color as brightness and two color difference signals, while RGB represents color as red, green and blue. In YCbCr, the Y is the brightness (luma), Cb is blue minus luma (B-Y) and Cr is red minus luma (R-Y).