Accelerate your wireless base station layer-1 software using the Arm RAN Acceleration Library.
Arm RAN Acceleration Library is an optimized set of software routines to implement common signal processing functions in Radio Access Network (RAN) using Neoverse and Cortex-A Arm cores.
Software Defined Radio approach
Traditional wireless base stations are implemented using a combination of general-purpose processors, DSP, and dedicated hardware accelerators.
The Arm RAN Acceleration Library takes advantage of the SIMD vector extensions of high-performance Neoverse cores to enable fast development of Software Defined Radio components for 5G PHY.
Open RAN platform innovation
High performance math kernels and signal processing primitives from the Arm RAN Acceleration Library enable very flexible hardware accelerator and software splits for the design of 5G New Radio Layer-1 functionality.
This design flexibility enables power efficient and cost-optimized wireless base station implementations using Arm Neoverse cores.
- Complex floating point and integer datatypes supported for all math kernels
- Highly optimized implementations for Arm Neon pipelines
- Works on any Neoverse and Arm Cortex-A cores
View the release history, release notes, and EULA for the Arm RAN Acceleration Library.
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|Answered||reliability of Arm processors Latest yesterday by fixxxer||1 replies 224 views|
|Answered||TLB stage2 translation Latest yesterday by fixxxer||1 replies 139 views|
|Answered||Session resources from the Linaro Tech Days (virtual event) Latest yesterday by fixxxer||1 replies 719 views|
|Answered||LDR assembler Latest 15 days ago by Andy Neil||2 replies 185 views|
|Answered||Which ARM micro controller should I choose? Latest 1 months ago by raj_99||4 replies 896 views|
|Answered||How to remove "Undfined Symbol" error?? Latest 2 months ago by omkardixi||1 replies 476 views|