System IP for enterprise

Getting Started

Infrastructure level systems demand sustainable on-chip bandwidth measured in terabits per second, coupled with ECC and RAS features to maintain system integrity, whilst at the same time supporting high-bandwidth IOs such as encryption engines, PCIe, SATA and multi-gigabit ethernet. To ensure the effectiveness of infrastructure class Arm Cortex processors, the whole system needs to be optimized. The CoreLink CCN Cache Coherent Network product family is specifically designed for such system optimization, enabling high bandwidth Networking and Server applications featuring 4,8 or 12 CPU cluster coherency with configurable level 3 caches.

The CCN interconnect couples tightly with the CoreLink Enterprise DMC supporting DDR4 DRAMs at the same time as managing ECC and providing RAS functionality. CoreLink NIC Non-Coherent Network Interconnect provides low latency peripheral connection, whilst CoreLink Enterprise GIC manages and distributes interrupts across multiple clusters, and even manages MSI(-X) based interrupts from sources such as PCIe. CoreLink SMMU provides IO virtualisation functions by accelerating address translation in hardware. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization.

The net result is a secure, reliable system with non-blocking, free flowing data.


System IP Description

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

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CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

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Memory Controllers

High bandwidth and low latency access to memory across DDR3/4 memory types for best-in-class performance and power efficiency.

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System controllers

High performance IP blocks that perform critical functions within the SoC.

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IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, using configuration and integration to help designers build better SoCs.

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TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

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Enterprise System Example

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Community Forums

Answered IP Camera interface via STM32
  • Cortex-M
  • STM32F
  • Cortex-M4
1 votes 36887 views 8 replies Latest 8 days ago by Akash Kasturi Answer this
Answered spi flash 16MB not working 1 votes 9487 views 2 replies Latest 19 days ago by sridhar6994 Answer this
Answered response ordering at AXI4 slave
  • AXI4
0 votes 2199 views 4 replies Latest 1 months ago by rvora Answer this
Answered Can AHB3_Lite master send an unaligend address?
  • AMBA 4
  • AXI4
  • AHB-Lite
0 votes 1730 views 2 replies Latest 1 months ago by Oliver Beirne Answer this
Answered AHB DeadLock: HREADY=0 & HTRANS=BUSY 0 votes 1836 views 3 replies Latest 1 months ago by Oliver Beirne Answer this
Discussion IDE Recommendation
  • Cortex-M3
  • IDEs and Tool Suites
  • Cortex-M
0 votes 7156 views 6 replies Latest 1 months ago by Andy Neil Answer this
Answered IP Camera interface via STM32 Latest 8 days ago by Akash Kasturi 8 replies 36887 views
Answered spi flash 16MB not working Latest 19 days ago by sridhar6994 2 replies 9487 views
Answered response ordering at AXI4 slave Latest 1 months ago by rvora 4 replies 2199 views
Answered Can AHB3_Lite master send an unaligend address? Latest 1 months ago by Oliver Beirne 2 replies 1730 views
Answered AHB DeadLock: HREADY=0 & HTRANS=BUSY Latest 1 months ago by Oliver Beirne 3 replies 1836 views
Discussion IDE Recommendation Latest 1 months ago by Andy Neil 6 replies 7156 views