System IP for enterprise

Getting Started

Infrastructure level systems demand sustainable on-chip bandwidth measured in terabits per second, coupled with ECC and RAS features to maintain system integrity, whilst at the same time supporting high-bandwidth IOs such as encryption engines, PCIe, SATA and multi-gigabit ethernet. To ensure the effectiveness of infrastructure class Arm Cortex processors, the whole system needs to be optimized. The CoreLink CCN Cache Coherent Network product family is specifically designed for such system optimization, enabling high bandwidth Networking and Server applications featuring 4,8 or 12 CPU cluster coherency with configurable level 3 caches.

The CCN interconnect couples tightly with the CoreLink Enterprise DMC supporting DDR4 DRAMs at the same time as managing ECC and providing RAS functionality. CoreLink NIC Non-Coherent Network Interconnect provides low latency peripheral connection, whilst CoreLink Enterprise GIC manages and distributes interrupts across multiple clusters, and even manages MSI(-X) based interrupts from sources such as PCIe. CoreLink SMMU provides IO virtualisation functions by accelerating address translation in hardware. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization.

The net result is a secure, reliable system with non-blocking, free flowing data.


System IP Description

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

Learn more

CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

Learn more

Memory Controllers

High bandwidth and low latency access to memory across DDR3/4 memory types for best-in-class performance and power efficiency.

Learn more

System controllers

High performance IP blocks that perform critical functions within the SoC.

Learn more

IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, using configuration and integration to help designers build better SoCs.

Learn more

TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

Learn more

Enterprise System Example

Get support

Community Forums

Answered ARM vs Thumb vs Thumb2 instruction set
  • T32 (Thumb)
0 votes 9830 views 2 replies Latest 16 days ago by Kevin B Answer this
Answered ARM/THUMB instructions that change execution path?
  • Thumb
0 votes 63055 views 77 replies Latest 17 days ago by jakebunt Answer this
Answered AMBA 5 CHI Link Layer (L-Credit Return)
  • AMBA 5 CHI
  • CHI
  • Cache Coherent Interconnect
  • AMBA 5
0 votes 3207 views 3 replies Latest 23 days ago by Christopher Tory Answer this
Answered Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model?
  • AXI4
0 votes 1703 views 1 replies Latest 25 days ago by Christopher Tory Answer this
Answered strobe 0 votes 7602 views 3 replies Latest 1 months ago by Christopher Tory Answer this
Answered AXI4-Relationships between the channels 0 votes 2984 views 1 replies Latest 1 months ago by Colin Campbell Answer this
Answered ARM vs Thumb vs Thumb2 instruction set Latest 16 days ago by Kevin B 2 replies 9830 views
Answered ARM/THUMB instructions that change execution path? Latest 17 days ago by jakebunt 77 replies 63055 views
Answered AMBA 5 CHI Link Layer (L-Credit Return) Latest 23 days ago by Christopher Tory 3 replies 3207 views
Answered Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model? Latest 25 days ago by Christopher Tory 1 replies 1703 views
Answered strobe Latest 1 months ago by Christopher Tory 3 replies 7602 views
Answered AXI4-Relationships between the channels Latest 1 months ago by Colin Campbell 1 replies 2984 views