Getting Started

TrustZone system IP blocks support the Arm TrustZone system-wide approach to security for preventing access by malicious software to memory regions and peripherals such as keyboards and screens. There are three products in this category.


TrustZone Controllers

TZC-400

CoreLink TZC-400 TrustZone Address Space Controller extends on-chip security to protect multiple regions of external memory from software attacks. It is compatible with CCI-400, NIC-400, and DMC-400 product families.

Click to view the TZC-400 TRM

BP147

PrimeCell BP147 TrustZone Protection Controller enables the Secure and Non-secure worlds to safely share peripherals. It supports an APB interface that is common to most I/O peripherals.

Click to view the BP147 TRM

BP141

PrimeCell BP141 TrustZone Internal Memory Wrapper manages a single Secure region with on-chip SRAM memory

Click to view the BP141 TRM

Start designing now

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Community Forums

Answered What happens to the Instructions already in pipeline when interrupt occurs ?
  • Software
  • Cortex-M0
  • Cortex-M0+
  • Interrupt
0 votes 374 views 6 replies Latest 4 days ago by 42Bastian Schick Answer this
Answered Cortex M0+, AHB state during Exception
  • Cortex-M0+
  • AHB
0 votes 133 views 1 replies Latest 6 days ago by 42Bastian Schick Answer this
Answered cortex m7 STR fail 0 votes 336 views 6 replies Latest 9 days ago by 42Bastian Schick Answer this
Answered Invalid Exception Class
  • Cortex-A53
  • AArch64
0 votes 2166 views 2 replies Latest 10 days ago by Killbox Answer this
Answered Normal Memory ordering & precise state question 0 votes 2015 views 3 replies Latest 10 days ago by ianl Answer this
Answered Programming BRAM with JTAG--Help regarding knowledge source requested.
  • Cortex-M0
  • JTAG
  • SWD
  • Memory
0 votes 314 views 4 replies Latest 10 days ago by Mezan1 Answer this
Answered What happens to the Instructions already in pipeline when interrupt occurs ? Latest 4 days ago by 42Bastian Schick 6 replies 374 views
Answered Cortex M0+, AHB state during Exception Latest 6 days ago by 42Bastian Schick 1 replies 133 views
Answered cortex m7 STR fail Latest 9 days ago by 42Bastian Schick 6 replies 336 views
Answered Invalid Exception Class Latest 10 days ago by Killbox 2 replies 2166 views
Answered Normal Memory ordering & precise state question Latest 10 days ago by ianl 3 replies 2015 views
Answered Programming BRAM with JTAG--Help regarding knowledge source requested. Latest 10 days ago by Mezan1 4 replies 314 views