The System Memory Management Unit family
White paper: Enterprise Virtualization with Arm CoreLink SMMU and Arm CoreLink GIC
CoreLink MMU-600AE features
- Meets automotive safety requirements for building high-performance ASIL B to ASIL D systems.
- Software compatible with MMU-600 with Arm v8.2 compliant RAS reporting interface.
- Efficient functional logic duplication, ECC and address protection for SRAM.
- AMBA extensions for interface protection.
- Fault management unit to simplify error reporting, testing and integration.
CoreLink MMU-600 features
- Enhances CoreLink MMU-500 feature set by incorporating SMMUv3.1 specification to support Armv8.2 CPUs.
- Expands the number of contexts supported to millions.
- Implements AMBA-DTI to interface TBU and TCU to improve scalability.
- Multi-level TLB and Walk Cache improves system address translation hit rates.
- Improved write buffer depth and parallel translations.
CoreLink MMU-500 Features
- Builds on top of MMU-400 features by implementing SMMUv2 architecture adding support for Armv8 CPUs.
- Supports Stage 1, Stage 2, and Stage1 followed by Stage 2 address translation for up to 128 active device contexts.
- Implements a distributed Translation Buffer Unit (TBU) micro-architecture with direct point-to-point connections between each TBU and the centralized Translation Control Unit (TCU) for Page Table Walks (PTWs).
- Supports up to 128 entries per TLB which is further backed by TCU cache up to 2K entries.
CoreLink MMU-401 Features
- Supports SMMUv1 architecture for Armv7 CPUs and Arm v8 for 64KB page sizes.
- Performs stage2 translation only for hypervisor support.
- Implements a single TBU micro-architecture with connection to a single TCU for page table walks.
CoreLink MMU-500 Characteristics
The CoreLink MMU-500 supports the translation formats of Armv7 and Armv8 architectures and performs Stage 1, Stage 2, or Stage 1 followed by Stage 2 translations for all page sizes except 16KB page granule for Armv8. The MMU-500 is implemented as a distributed design with one or more TBUs communicating to a single centralized TCU that performs PTWs to memory. Each TBU can be located in its own clock and power domain making it easy to co-locate the TBU with the peripheral requiring translation. Each TBU communicates to the TCU over an point-to-point stream interface and with bus masters over ACE-Lite. The TCU has an AXI4 slave interface for configuration.
Get support with Arm Training courses and design reviews. You can also open a support case or manage existing cases.
|Suggested answer||Which ARM board will be most suitable?||0 votes||1648 views||3 replies||Latest 17 hours ago by Dharmalingam.K||Answer this|
|Suggested answer||In AXI Why there is a read response in each data transfer?||0 votes||5377 views||4 replies||Latest yesterday by Jenniferl||Answer this|
|Not answered||Making ONVIF conformant surveillance camera with STM32H743.||0 votes||62 views||0 replies||Started yesterday by Akash Kasturi||Answer this|
|Answered||IP Camera interface via STM32||1 votes||36218 views||8 replies||Latest yesterday by Akash Kasturi||Answer this|
|Not answered||LPC2138 Program Execution Issue||0 votes||98 views||0 replies||Started yesterday by kishor potdar||Answer this|
|Suggested answer||Hard fault handler problem - Cortex-M0+||0 votes||439 views||1 replies||Latest 6 days ago by Clonimus74||Answer this|
|Suggested answer||Which ARM board will be most suitable? Latest 17 hours ago by Dharmalingam.K||3 replies 1648 views|
|Suggested answer||In AXI Why there is a read response in each data transfer? Latest yesterday by Jenniferl||4 replies 5377 views|
|Not answered||Making ONVIF conformant surveillance camera with STM32H743. Started yesterday by Akash Kasturi||0 replies 62 views|
|Answered||IP Camera interface via STM32 Latest yesterday by Akash Kasturi||8 replies 36218 views|
|Not answered||LPC2138 Program Execution Issue Started yesterday by kishor potdar||0 replies 98 views|
|Suggested answer||Hard fault handler problem - Cortex-M0+ Latest 6 days ago by Clonimus74||1 replies 439 views|