Static Memory Controllers

The Arm CoreLink Static Memory Controllers

Static Memory Controller Block Diagram.

Getting Started

Static or Non-volatile memory is typically a shared resource to which many different masters and processes require access. Effective, error-free access to static memory is important for both system performance and system power.

The CoreLink Static Memory Controllers (SMC) provide efficient interfaces to a wide range of types of non-volatile memory, applying the features of AMBA AXI to schedule requests to the memory in the most optimal way. They are designed for compatibility with the Arm portfolio of Memory ControllersCoreLink Interconnect and Processor solutions emphasizing low-power and high-performance operation.


Why choose a CoreLink Static Memory Controller?

Most systems with Arm processors have off-chip static (non-volatile) memories. These contain information such as object code and data files. System performance depends on being able to read and write this data efficiently and accurately. CoreLink Static Memory Controllers are available for AMBA AXI (SMC-35X) and AMBA AHB (PL24X). These controllers are optimized for the bus protocol and have been developed to complement the CoreLink Network Interconnect, and Dynamic Memory Controllers along with Arm CPU and media processors.

Verification and Benchmarking

Understanding the performance and functionality of the memory controller in a system context is critical to the specification and development of the controller. The system level verification and benchmarking ensure the delivery of products that have been fully qualified alongside the cores and on-chip interconnect. These results then drive the specifications of both current and future memory controllers. They ensure efficient, low-risk, easy to integrate solutions that enable development to proceed smoothly - meeting performance goals and delivering time to market.

And for the future?

Arm is committed to ensuring the Arm ecosystem has the memory controller solutions in demand. Arm participates in the industry standards bodies defining new memory interfaces. Collaboration with Arm teams developing new cores and new interconnects ensures that memory interface support for new products is available when needed.

How to choose

AXI Static Memory Controllers

The SMC-35X family of products provides an interface between AXI interconnects and a range of non-volatile memories. The SMC-35X has a wide range of configurable parameters, these are described under the specifications tab. 

Product

Non-Volatile Memory Supported

Notes

SMC-351

NAND Flash

up to 4 chip selects

SMC-352

NOR Flash / SRAM

up to 4 chip selects

SMC-353

NAND Flash and NOR Flash / SRAM

up to 4 NAND and 4 NOR/SRAM

SMC-354

NOR Flash / SRAM

up to 8 chip selects in 2 groups of 4


AHB Memory Controllers

The PL24X family products provide an interface between AHB interconnects and non-volatile memory. These are hybrid controllers also providing an interface to DRAM memory systems.

Other combinations of memory can be supported by using a combination of the CoreLink Network Interconnect product with DMC-34X and SMC-35X memory controllers.


 Product NV Memory Supported  DRAM Support  AHB Ports 
 PL241 NOR/SRAM  None  1
 PL242 NAND  SDR  4
 PL243 NOR/SRAM  SDR  4
 PL244 NAND  DDR  6
 PL245 NOR/SRAM  DDR  6

Other combinations of memory can be supported by using a combination of the CoreLink Network Interconnect product with DMC-34X and SMC-35X memory controllers.

 

Get support

Community Forums

Suggested answer Hard fault handler problem - Cortex-M0+
  • R13 (SP Stack Pointer)
  • 3 (HardFault)
0 votes 894 views 4 replies Latest 10 hours ago by Clonimus74 Answer this
Suggested answer After first execution control goes to task 2 but i want him to go to task1 what i suppose to do here?
  • Real Time Operating Systems (RTOS)
0 votes 457 views 1 replies Latest 4 days ago by fixxxer Answer this
Suggested answer Is there any extra parameter needed to start networking on FVP_MPS2_M7 simulator?
  • Embedded Software
  • Cortex-M7
  • Simulation
  • Cortex-M3
  • networking
  • Fast Models
  • Cortex-M7 FVP
0 votes 1162 views 1 replies Latest 4 days ago by fixxxer Answer this
Suggested answer L1 cache BW 0 votes 589 views 2 replies Latest 4 days ago by fixxxer Answer this
Suggested answer Making ONVIF conformant surveillance camera with STM32H743.
  • stm32 h7
0 votes 1085 views 5 replies Latest 6 days ago by ibrahim1236 Answer this
Suggested answer Which ARM board will be most suitable?
  • Video Processor Embedded Algorithms
  • Video Processor
0 votes 1940 views 3 replies Latest 8 days ago by Dharmalingam.K Answer this
Suggested answer Hard fault handler problem - Cortex-M0+ Latest 10 hours ago by Clonimus74 4 replies 894 views
Suggested answer After first execution control goes to task 2 but i want him to go to task1 what i suppose to do here? Latest 4 days ago by fixxxer 1 replies 457 views
Suggested answer Is there any extra parameter needed to start networking on FVP_MPS2_M7 simulator? Latest 4 days ago by fixxxer 1 replies 1162 views
Suggested answer L1 cache BW Latest 4 days ago by fixxxer 2 replies 589 views
Suggested answer Making ONVIF conformant surveillance camera with STM32H743. Latest 6 days ago by ibrahim1236 5 replies 1085 views
Suggested answer Which ARM board will be most suitable? Latest 8 days ago by Dharmalingam.K 3 replies 1940 views