Getting Started

AMBA system controllers are a collection of controller IP that Arm offers. These controllers are for Direct Memory Access (DMA), Level 2 Cache, and peripherals. These controllers are low-power, high-performance IP cores that perform critical tasks within the AMBA system. Designed for optimal compatibility with Arm Cortex, Mali multimedia, and CoreLink System IP, they are the natural complement to interconnect and memory controllers.


DMA controllers

The Direct Memory Access (DMA) controller enables the movement of blocks of data from peripheral to memory, memory to peripheral, or memory to memory without burdening the processor. Efficient use of DMA can significantly improve system performance in multiple dimensions. For example, using a DMA controller can offload a processor and either reduce power consumption, or boost the processor performance, or a combination of both. AMBA DMA controllers are designed to complement both high-end and energy-efficient systems. They provide a centralized DMA processing capability that is high performance and highly flexible, and at the same time, is area efficient. Key product offerings for DMA controllers are: 

  • CoreLink DMA-330: The DMA-330 is a high-performance DMA controller that can boost the performance and reduce the power consumption in AXI systems.  The DMA-330 is a highly configurable device to support a wide range of applications and architectures.  The DMA-330 is programmable to support scatter-gather, memory to memory, peripheral to memory, and memory to peripheral transfers, run-from-reset, security on channels, interrupts, and peripherals.

    Click to view the DMA-330 TRM.

  • PrimeCell Micro DMA-230: The DMA-230 is a low gate count (3-10k gates) micro-DMA engine targeting Cortex-M3 systems and other low-power and cost-sensitive applications. The device offers excellent performance at low gate count and all the code is stored in system RAM rather than in registers. Using this component enables Cortex-M1 and Cortex-M3 based systems to remain low cost through reduced gate count and enabling scaling down the frequency of the processor in the system for reducing overall power consumption.

    Click to view the DMA-230 TRM.

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Suggested answer DC/DC Controller SoC 0 votes 287 views 1 replies Latest 3 days ago by Andy Neil Answer this
Suggested answer AMBA 5 CHI : Does Interleaving of TxnID within a Multiple flits message allowed?
  • System on Chip (SoC)
  • AMBA 5 CHI
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  • Cache Architecture
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Answered ARM vs Thumb vs Thumb2 instruction set
  • T32 (Thumb)
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Answered ARM/THUMB instructions that change execution path?
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Not answered ACE-Lite 0 votes 343 views 0 replies Started 8 days ago by Ishan Answer this
Not answered Porting to U-boot driver model and device tree control (for ARM-based design)
  • Peripheral Devices
  • U-Boot
0 votes 522 views 0 replies Started 10 days ago by Rob Damico Answer this
Suggested answer DC/DC Controller SoC Latest 3 days ago by Andy Neil 1 replies 287 views
Suggested answer AMBA 5 CHI : Does Interleaving of TxnID within a Multiple flits message allowed? Latest 6 days ago by IPDeveloper 1 replies 436 views
Answered ARM vs Thumb vs Thumb2 instruction set Latest 7 days ago by Kevin B 2 replies 9022 views
Answered ARM/THUMB instructions that change execution path? Latest 8 days ago by jakebunt 77 replies 61908 views
Not answered ACE-Lite Started 8 days ago by Ishan 0 replies 343 views
Not answered Porting to U-boot driver model and device tree control (for ARM-based design) Started 10 days ago by Rob Damico 0 replies 522 views