Overview

The Arm CoreLink System Controllers

Arm CoreLink System Controllers orchestrate critical AMBA system tasks such as hardware virtualization support, interrupt management, L3 cache operation, DMA, TrustZone security and peripheral operation. Designed for optimal compatibility with Arm processors and Multimedia IP, they are the natural complements to the System IP Interconnect and Memory Controller product lines. 

Use Cases

System Controllers are used for many functions within an SoC, including:

Virtualization

Virtualization is the ability of a system to support multiple virtual machines each running its own guest operating system with its own private access to memory and IO peripherals without any interference whatsoever from the others. Arm's SMMU enables hardware virtualization by performing stage1 and/or stage2 address translation for IO devices, thereby providing them with the same view of memory as the CPU/GPU. 


Memory Mapping

Another interesting use case of SMMU is to perform memory mapping to enable a programmable view of memory for IO peripherals. As an example, SMMU supports scatter-gather operations whereby an IO peripheral can access disjoint locations of physical memory as a single contiguous block of virtual memory due to the SMMU translation. This results in improved utilization of memory while ensuring that the IO peripheral performance is not affected. 


Cache Control

CPU to off-chip memory communication has become the performance bottleneck in many SoCs. Level 2 Cache Controllers improve CPU performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip. At the same time, the reduced CPU demands on the off-chip memory bandwidth free up that resource for other masters. Level 2 Cache Controllers also contribute significantly to power efficiency as on-chip accesses are typically an order of magnitude lower in power versus going off-chip. Typically these are embedded inside the CPU or delivered as standalone components optimized to match the processor requirements and integrate easily into the AMBA interconnect.


Interrupt Management & Translation

Arm GICs perform the key function of interrupt management and translation. Management functions include detection, masking, prioritization and routing of interrupts to the appropriate cores. Interrupt Translation Service (ITS) modules in the GIC perform the task of device isolation and ID translation for incoming message-based interrupts, thereby enabling virtual machines to program peripherals directly.


Security

Arm's TrustZone security platform enables hardware-based secure access to regions of both off-chip memory and on-chip SRAM. The memory space is divided into a configurable number of regions each with its own access permissions. This setup ensures that malicious software cannot compromise system operation by latching onto data or code it shouldn't have access to. 


Direct Access to Memory

Arm's CoreLink DMA controllers perform critical functions of moving streams of data between a peripheral and memory without overloading the CPU. Software programs typically write the data transfer instructions to memory and trigger the DMA engine which then takes over and performs the data move without incurring any additional overhead on the CPU.

 

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Not answered Which ARM board will be most suitable? Started 15 hours ago by Surya 0 replies 60 views
Suggested answer test cases for apb Latest 21 hours ago by Colin Campbell 3 replies 322 views
Suggested answer what is different that change start address and use WSTRB signal for transfer Latest yesterday by Colin Campbell 1 replies 240 views
Suggested answer why use unaligned transfers in AXI Latest yesterday by Colin Campbell 1 replies 215 views
Suggested answer What purpose does SINGLE BURST feature in AHB serve? Latest 3 days ago by Colin Campbell 1 replies 224 views
Suggested answer How feasible and what is the API for packet filtering at harware level (using Trust zone)? Latest 6 days ago by Oliver Beirne 1 replies 591 views