Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).
CoreLink DMC-520 Dynamic Memory Controller
- Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family
CoreLink DMC-620 Dynamic Memory Controller
- Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
- Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
- Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.
Documents and blogs that will help users design Arm-based SoCs
Get support with Arm Training courses and design reviews. You can also open a support case or manage existing cases.
|Suggested answer||I2C problem on Cypress PSoC3 (with EEPROM and FRAM too)||0 votes||5211 views||5 replies||Latest yesterday by Andy Neil||Answer this|
|Suggested answer||application which takes audio input from uart and give text output||1 votes||3863 views||1 replies||Latest 2 days ago by verduy||Answer this|
|Suggested answer||JTAG/SWD and entering debug monitor||0 votes||4227 views||2 replies||Latest 3 days ago by vaiyawa||Answer this|
|Suggested answer||how to covert Speech to text||1 votes||5827 views||2 replies||Latest 3 days ago by vaiyawa||Answer this|
|Not answered||AHB Lite||0 votes||314 views||0 replies||Started 5 days ago by Jenish Radadiya||Answer this|
|Suggested answer||Design considerations for implementing flash program download||0 votes||5931 views||3 replies||Latest 5 days ago by Mohamed Nasser||Answer this|
|Suggested answer||I2C problem on Cypress PSoC3 (with EEPROM and FRAM too) Latest yesterday by Andy Neil||5 replies 5211 views|
|Suggested answer||application which takes audio input from uart and give text output Latest 2 days ago by verduy||1 replies 3863 views|
|Suggested answer||JTAG/SWD and entering debug monitor Latest 3 days ago by vaiyawa||2 replies 4227 views|
|Suggested answer||how to covert Speech to text Latest 3 days ago by vaiyawa||2 replies 5827 views|
|Not answered||AHB Lite Started 5 days ago by Jenish Radadiya||0 replies 314 views|
|Suggested answer||Design considerations for implementing flash program download Latest 5 days ago by Mohamed Nasser||3 replies 5931 views|