Getting Started

Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).

The Dynamic Memory Controller family

CoreLink DMC-500 Dynamic Memory Controller

CoreLink DMC-500 Dynamic Memory Controller

  • Specifically designed for low power operation in mobile, consumer and embedded applications that utilize LPDDR4 and LPDDR3 memories
  • Optimized for best memory bandwidth at low latencies with Arm CoreLink CCI and NIC




CoreLink DMC-520 Dynamic Memory Controller

CoreLink DMC-520 Dynamic Memory Controller

  • Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories
  • Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family


DMC-620

CoreLink DMC-620 Dynamic Memory Controller

  • Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
  • Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
  • Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.


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Suggested answer AXI4 master requirements for unaligned transactions (address v/s WSTRB) 0 votes 94 views 1 replies Latest 11 hours ago by guimers8 Answer this
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Not answered Missing CoreSight components in /renensas/r8a77970.dtsi
  • CoreSight Trace Funnel
  • replicator
  • TPIU
  • AMBA 3 ATB Interface
  • CoreSight System Trace Macrocell (STM)
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Not answered I am working on AXI vip and I am confused about where should I put logic about burst(FIXED,INCR,WRAP) can anybody give me direction ?
  • AXI4
0 votes 64 views 0 replies Started 2 days ago by pure Answer this
Not answered AMBA 5 CHI Coherance protocol details 0 votes 140 views 0 replies Started 5 days ago by JO16 Answer this
Answered Atomic access LDR/STR vs LDREX/STREX
  • AHB-Lite
  • DesignStart
0 votes 659 views 2 replies Latest 6 days ago by EBB Answer this
Suggested answer AXI4 master requirements for unaligned transactions (address v/s WSTRB) Latest 11 hours ago by guimers8 1 replies 94 views
Not answered TFT/LCD graphic contoller Started 15 hours ago by levetop 0 replies 102 views
Not answered Missing CoreSight components in /renensas/r8a77970.dtsi Started yesterday by LWT 0 replies 46 views
Not answered I am working on AXI vip and I am confused about where should I put logic about burst(FIXED,INCR,WRAP) can anybody give me direction ? Started 2 days ago by pure 0 replies 64 views
Not answered AMBA 5 CHI Coherance protocol details Started 5 days ago by JO16 0 replies 140 views
Answered Atomic access LDR/STR vs LDREX/STREX Latest 6 days ago by EBB 2 replies 659 views