Getting Started

Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).

The Dynamic Memory Controller family

CoreLink DMC-500 Dynamic Memory Controller

CoreLink DMC-500 Dynamic Memory Controller

  • Specifically designed for low power operation in mobile, consumer and embedded applications that utilize LPDDR4 and LPDDR3 memories
  • Optimized for best memory bandwidth at low latencies with Arm CoreLink CCI and NIC




CoreLink DMC-520 Dynamic Memory Controller

CoreLink DMC-520 Dynamic Memory Controller

  • Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories
  • Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family


DMC-620

CoreLink DMC-620 Dynamic Memory Controller

  • Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
  • Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
  • Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.


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Community Blogs

Community Forums

Not answered CCN-502 profiling: how do I know which port HN-F is attached to? 0 votes 136 views 0 replies Started yesterday by Oscar Huang Answer this
Not answered outsanading behaviour in AXI Vs memory latency
  • AMBA 4
  • AMBA 3 AXI Interface
0 votes 365 views 0 replies Started 3 days ago by vereng Answer this
Suggested answer ARM AMBA AXI4 read channel information
  • AXI4
0 votes 965 views 1 replies Latest 4 days ago by Colin Campbell Answer this
Suggested answer stm32h753 rtc resets after power down (vbat is connected)
  • STM32
0 votes 1204 views 1 replies Latest 5 days ago by Andy Neil Answer this
Suggested answer I2C problem on Cypress PSoC3 (with EEPROM and FRAM too) 0 votes 856 views 3 replies Latest 5 days ago by Andy Neil Answer this
Answered outstanding transaction in AXI4 protocol 0 votes 8279 views 4 replies Latest 7 days ago by Colin Campbell Answer this
Not answered CCN-502 profiling: how do I know which port HN-F is attached to? Started yesterday by Oscar Huang 0 replies 136 views
Not answered outsanading behaviour in AXI Vs memory latency Started 3 days ago by vereng 0 replies 365 views
Suggested answer ARM AMBA AXI4 read channel information Latest 4 days ago by Colin Campbell 1 replies 965 views
Suggested answer stm32h753 rtc resets after power down (vbat is connected) Latest 5 days ago by Andy Neil 1 replies 1204 views
Suggested answer I2C problem on Cypress PSoC3 (with EEPROM and FRAM too) Latest 5 days ago by Andy Neil 3 replies 856 views
Answered outstanding transaction in AXI4 protocol Latest 7 days ago by Colin Campbell 4 replies 8279 views