System Trace Macrocell

Getting Started

The Arm CoreSight System Trace Macrocell (STM) is a trace source that enables real-time instrumentation of software with no impact on system behavior or performance. For software, system and hardware engineers, visibility of the complete system is now critical. This is due to the need to deliver high performance, power optimized systems in shorter development cycles.

The Arm CoreSight System Trace Macrocell (STM) extends low-cost real-time visibility of software and hardware execution to all software developers. In particular application and kernel developers, enabling rich, optimized and low power software on Arm processor-powered devices across the whole supply chain.

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.


  • A program that is running on a desktop.
  • CoreSight technical introduction

    Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.

    Read here
  • A program that is running on a desktop.
  • Introduction to CoreSight SoC-400

    This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.

    Watch video
  • A program that is running on a desktop.
  • Better trace for better software with Arm CoreSight

    This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.

    Read here
  • A program that is running on a desktop.
  • Low pin-count debug interfaces for multi-device systems

    This white paper examines some alternatives to JTAG as a debug interface, and concludes that a serial wire debug interface can be delivered with lower pin-count and higher performance, and maintain support for multiprocessor systems and interoperability with test.

    Read here
  • A development Board.
  • Key steps to create a debug and trace solution for an Arm SoC

    The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.

    Read here

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Community Forums

Suggested answer Which ARM board will be most suitable?
  • Video Processor Embedded Algorithms
  • Video Processor
0 votes 1648 views 3 replies Latest 17 hours ago by Dharmalingam.K Answer this
Suggested answer In AXI Why there is a read response in each data transfer? 0 votes 5376 views 4 replies Latest yesterday by Jenniferl Answer this
Not answered Making ONVIF conformant surveillance camera with STM32H743.
  • stm32 h7
0 votes 62 views 0 replies Started yesterday by Akash Kasturi Answer this
Answered IP Camera interface via STM32
  • Cortex-M
  • STM32F
  • Cortex-M4
1 votes 36216 views 8 replies Latest yesterday by Akash Kasturi Answer this
Not answered LPC2138 Program Execution Issue 0 votes 98 views 0 replies Started yesterday by kishor potdar Answer this
Suggested answer Hard fault handler problem - Cortex-M0+
  • R13 (SP Stack Pointer)
  • 3 (HardFault)
0 votes 439 views 1 replies Latest 6 days ago by Clonimus74 Answer this
Suggested answer Which ARM board will be most suitable? Latest 17 hours ago by Dharmalingam.K 3 replies 1648 views
Suggested answer In AXI Why there is a read response in each data transfer? Latest yesterday by Jenniferl 4 replies 5376 views
Not answered Making ONVIF conformant surveillance camera with STM32H743. Started yesterday by Akash Kasturi 0 replies 62 views
Answered IP Camera interface via STM32 Latest yesterday by Akash Kasturi 8 replies 36216 views
Not answered LPC2138 Program Execution Issue Started yesterday by kishor potdar 0 replies 98 views
Suggested answer Hard fault handler problem - Cortex-M0+ Latest 6 days ago by Clonimus74 1 replies 439 views