CoreSight STM-500

CoreSigh STM-500 Chip.

Getting Started

The STM-500 is a trace source that is integrated into a CoreSight system. CoreSight STM-500 is designed for high-bandwidth trace of instrumentation embedded into software. STM Advanced eXtensible Interface (AXI) slave is made up of memory-mapped writes, which carry information about the behavior of the software.

CoreSight STM-500 is a natural successor to the CoreSight Instrumentation Trace Macrocell (ITM) in mid- to high-performance applications.


CoreSight STM-500 Features

CoreSight STM-500 has the following features:

  • A fully synchronous design with one clock and two resets
  • One 64-bit AXI slave interface for extended stimulus port inputs
  • One hardware event observation interface for tracing 64 hardware events
  • One 32-bit debug APB slave interface for configuration and status
  • One 64-bit ATB slave interface for configuration and status
  • One DMA peripheral request interface that is compatible with the AMBA DMA Controller DMA-330
  • Two depth-configurable FIFO buffers for usage-optimized configurability:
    • Data FIFO
    • Channel information FIFO
  • A fully memory-mapped software stimulus supporting 65,536 stimulus ports and 128 masters
  • Leading zero data compression
  • Full support for guaranteed and invariant timing software stimulus writes
  • Support for single-shot and multi-shot triggers with a cross-trigger port, trigger packet insertion, and ATB trace triggers
  • An internal and an external source for STPv2 synchronization
  • Timestamping of trace events
  • Two low-power interfaces

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

  • A line drawing of a book.
  • CoreSight STM-500 Technical Reference Manual

     

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CoreSight STM-500 Community Blogs

CoreSight STM-500 Community Forums

Answered ARM vs Thumb vs Thumb2 instruction set
  • T32 (Thumb)
0 votes 9830 views 2 replies Latest 16 days ago by Kevin B Answer this
Answered ARM/THUMB instructions that change execution path?
  • Thumb
0 votes 63059 views 77 replies Latest 17 days ago by jakebunt Answer this
Answered AMBA 5 CHI Link Layer (L-Credit Return)
  • AMBA 5 CHI
  • CHI
  • Cache Coherent Interconnect
  • AMBA 5
0 votes 3207 views 3 replies Latest 24 days ago by Christopher Tory Answer this
Answered Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model?
  • AXI4
0 votes 1703 views 1 replies Latest 25 days ago by Christopher Tory Answer this
Answered strobe 0 votes 7602 views 3 replies Latest 1 months ago by Christopher Tory Answer this
Answered AXI4-Relationships between the channels 0 votes 2984 views 1 replies Latest 1 months ago by Colin Campbell Answer this
Answered ARM vs Thumb vs Thumb2 instruction set Latest 16 days ago by Kevin B 2 replies 9830 views
Answered ARM/THUMB instructions that change execution path? Latest 17 days ago by jakebunt 77 replies 63059 views
Answered AMBA 5 CHI Link Layer (L-Credit Return) Latest 24 days ago by Christopher Tory 3 replies 3207 views
Answered Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model? Latest 25 days ago by Christopher Tory 1 replies 1703 views
Answered strobe Latest 1 months ago by Christopher Tory 3 replies 7602 views
Answered AXI4-Relationships between the channels Latest 1 months ago by Colin Campbell 1 replies 2984 views