The Arm CoreSight SDC-600 Secure Debug Channel, provides a dedicated path to a debugged system for authenticating debug accesses. Key benefits include:
- A standardized communication protocol
- The first layer of protection against debug access attacks
- Robust security solution with Arm Security IP
|Conventional Secure JTAG Controller||CoreSight SDC-600|
|Need for external JTAG pins exposure||Functional IO/JTAG pins|
|Simple key-based authentication||Certificate and key-based authentication|
|No / lack of cryptographic involvement||Fully interoperable with Crypto IP|
|Customized communication protocol||Standard and open communication protocol|
Start designing now
Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.
Authenticated debug through an always-on communication channel
CoreSight SDC-600 addresses the security needs of modern day devices, by allowing silicon and tool vendors to enforce protection and to police debug accesses into the system. This is achieved through a debug certificate, exchanged through a dedicated communication path of CoreSight SDC-600.
Complete end-to-end security solution
CoreSight SDC-600 is intended to work closely with Cryptographic elements, to provide a robust security solution through debug certificate authentication. Arm ensures that CoreSight SDC-600 is designed and tested, to work efficiently with Arm CoreSight IP and Arm Security IP. This provides the most reliable and predictable security implementation for authenticating debug accesses.
Promoting efficient ecosystem adoption
CoreSight SDC-600 implements the Arm recommended communication protocol, which enables efficient handshake communication between an external agent and target system.
Get support with Arm training courses and design reviews. You can also open a support case or manage existing cases.Arm training courses Arm Design Reviews Open a support case
|Suggested answer||Which ARM board will be most suitable?||0 votes||1648 views||3 replies||Latest 17 hours ago by Dharmalingam.K||Answer this|
|Suggested answer||In AXI Why there is a read response in each data transfer?||0 votes||5377 views||4 replies||Latest yesterday by Jenniferl||Answer this|
|Not answered||Making ONVIF conformant surveillance camera with STM32H743.||0 votes||62 views||0 replies||Started yesterday by Akash Kasturi||Answer this|
|Answered||IP Camera interface via STM32||1 votes||36218 views||8 replies||Latest yesterday by Akash Kasturi||Answer this|
|Not answered||LPC2138 Program Execution Issue||0 votes||98 views||0 replies||Started yesterday by kishor potdar||Answer this|
|Suggested answer||Hard fault handler problem - Cortex-M0+||0 votes||439 views||1 replies||Latest 6 days ago by Clonimus74||Answer this|
|Suggested answer||Which ARM board will be most suitable? Latest 17 hours ago by Dharmalingam.K||3 replies 1648 views|
|Suggested answer||In AXI Why there is a read response in each data transfer? Latest yesterday by Jenniferl||4 replies 5377 views|
|Not answered||Making ONVIF conformant surveillance camera with STM32H743. Started yesterday by Akash Kasturi||0 replies 62 views|
|Answered||IP Camera interface via STM32 Latest yesterday by Akash Kasturi||8 replies 36218 views|
|Not answered||LPC2138 Program Execution Issue Started yesterday by kishor potdar||0 replies 98 views|
|Suggested answer||Hard fault handler problem - Cortex-M0+ Latest 6 days ago by Clonimus74||1 replies 439 views|