The Arm CoreSight SDC-600 Secure Debug Channel

CoreSight SDC-600 Chip.

Getting Started

The Arm CoreSight SDC-600 Secure Debug Channel, provides a dedicated path to a debugged system for authenticating debug accesses. Key benefits include:

  • A standardized communication protocol
  • The first layer of protection against debug access attacks
  • Robust security solution with Arm Security IP

Specifications

Conventional Secure JTAG Controller CoreSight SDC-600
Need for external JTAG pins exposure Functional IO/JTAG pins
Simple key-based authentication Certificate and key-based authentication
No / lack of cryptographic involvement Fully interoperable with Crypto IP
Customized communication protocol Standard and open communication protocol

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

Key features

Authenticated debug through an always-on communication channel

CoreSight SDC-600 addresses the security needs of modern day devices, by allowing silicon and tool vendors to enforce protection and to police debug accesses into the system. This is achieved through a debug certificate, exchanged through a dedicated communication path of CoreSight SDC-600.

Complete end-to-end security solution

CoreSight SDC-600 is intended to work closely with Cryptographic elements, to provide a robust security solution through debug certificate authentication. Arm ensures that CoreSight SDC-600 is designed and tested, to work efficiently with Arm CoreSight IP and Arm Security IP. This provides the most reliable and predictable security implementation for authenticating debug accesses. 

Promoting efficient ecosystem adoption

CoreSight SDC-600 implements the Arm recommended communication protocol, which enables efficient handshake communication between an external agent and target system.

Get support

Community Blogs

Community Forums

Suggested answer I2C problem on Cypress PSoC3 (with EEPROM and FRAM too) 0 votes 5142 views 5 replies Latest 7 hours ago by Andy Neil Answer this
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Suggested answer JTAG/SWD and entering debug monitor
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Not answered AHB Lite 0 votes 295 views 0 replies Started 3 days ago by Jenish Radadiya Answer this
Suggested answer Design considerations for implementing flash program download
  • CoreSight Architecture
  • SWD
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0 votes 5888 views 3 replies Latest 4 days ago by Mohamed Nasser Answer this
Suggested answer I2C problem on Cypress PSoC3 (with EEPROM and FRAM too) Latest 7 hours ago by Andy Neil 5 replies 5142 views
Suggested answer application which takes audio input from uart and give text output Latest 9 hours ago by verduy 1 replies 3808 views
Suggested answer JTAG/SWD and entering debug monitor Latest yesterday by vaiyawa 2 replies 4189 views
Suggested answer how to covert Speech to text Latest yesterday by vaiyawa 2 replies 5781 views
Not answered AHB Lite Started 3 days ago by Jenish Radadiya 0 replies 295 views
Suggested answer Design considerations for implementing flash program download Latest 4 days ago by Mohamed Nasser 3 replies 5888 views