Arm CoreSight ELA-600 Embedded Logic Analyzer

CoreSight-ELA 600 Chip.

Getting Started

The CoreSight ELA-600 Embedded Logic Analyzer inherits the debug capability and signal observability features of CoreSight ELA-500 with further optimization to improve data tracing efficiency and capacity. With CoreSight ELA-600, trigger condition can be set to initiate data tracing or output actions.
You also have the option of either storing trace data within CoreSight ELA-600 embedded SRAM in the same manner as CoreSight ELA-500 or aggregating them onto a larger memory area in the system/external to the SoC. 

Benefits

  • Improve low-level signal observability and controllability in post-silicon debug.
  • Shorten debug cycle by speeding up error root-cause analysis.
  • Improve system efficiency with run-time signal monitoring and control.

Specifications

CoreSight ELA-600 allows you to identify hard-to-diagnose bugs quickly. This accelerates silicon bring-up.

ELA-600 schematic diagram showing 12 input group signals and main ELA-600 functions

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

CoreSight ELA-500 and ELA-600 Comparison

CoreSight ELA-600 gives you additional enhancements that extend existing debug and trace use cases.

Feature ELA-500 ELA-600
Trigger states 5 8
Embedded RAM config  ✔
 ✔
Data compression    ✔
ATB interface    ✔
Simultaneous trace of 2 SIGNALGRPs on same clock cycle    ✔
Trigger state counters tracing    ✔
32-bit segmented trigger state comparators    ✔


  • Manual containing technical information.
  • Technical Reference Manual

    For system designers, systems integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here

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Suggested answer I2C problem on Cypress PSoC3 (with EEPROM and FRAM too) 0 votes 5143 views 5 replies Latest 8 hours ago by Andy Neil Answer this
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  • CoreSight Architecture
  • SWD
  • Debug Access Port (DAP)
0 votes 5889 views 3 replies Latest 4 days ago by Mohamed Nasser Answer this
Suggested answer I2C problem on Cypress PSoC3 (with EEPROM and FRAM too) Latest 8 hours ago by Andy Neil 5 replies 5143 views
Suggested answer application which takes audio input from uart and give text output Latest 10 hours ago by verduy 1 replies 3810 views
Suggested answer JTAG/SWD and entering debug monitor Latest yesterday by vaiyawa 2 replies 4190 views
Suggested answer how to covert Speech to text Latest yesterday by vaiyawa 2 replies 5784 views
Not answered AHB Lite Started 3 days ago by Jenish Radadiya 0 replies 295 views
Suggested answer Design considerations for implementing flash program download Latest 4 days ago by Mohamed Nasser 3 replies 5889 views