Getting Started

Arm CoreSight technology is a set of tools that can be used to debug and trace software that runs on Arm-based SoCs. Debugging features are used to observe or modify the state of parts of the design, while trace features allow for continuous collection of system information for later off-line analysis. With CoreSight, both are used together at all stages in the design flow.

  • CoreSight Soc-600 Chip.
  • CoreSight Components

    • CoreSight SoC-600 
    • CoreSight SoC-400
    • System Trace Macrocell
    • Trace Memory Controller
    • CoreSight ELA-500
    • CoreSight ELA-600
    • CoreSight SDC-600
    Find out more
  • A bug (representing debugging).
  • CoreSight Architecture

    • Serial Wire Debug
    • Arm Debug Interface (ADI) Architecture
    • Architecture Specifications
    • High Speed Serial Trace Port

    Find out more

Tools Support

CoreSight debug and trace is fully supported by Arm Development Studio for the bring-up and optimization of SoCs. It is also supported by a wide array of software and hardware debug tools companies, across all markets and regions. Some examples are: 

  • Debug of symmetric multi-processing and asymmetric multicore systems with Arm Development Studio.
  • Powerful interactive debugging with real-time visibility with Green Hills' TimeMachine.
  • Performance optimization using actual best/worst/average execution times at the instruction, block, function and task levels with Streamline.

Highlights 

CoreSight IP provides all the components needed to generate a debug and trace solution that also includes cross trigger and time-stamping distribution capabilities, as well as embedded logic analysis and system trace.

CoreSight SoC components

The CoreSight SoC components provide all the infrastructure required at the SoC level for building a complete debug and trace infrastructure for single and multi-processing units, such as Cortex processors. Arm offers a public CoreSight architecture specification describing standard interfaces and programmer views; this enables developers to integrate their debug and trace solution within the Arm CoreSight solution.

The CoreSight technology offers an exhaustive range of trace macrocells including:

  • CoreSight Embedded Trace Macrocells (ETM)
  • Program Trace Macrocells (PTM)
  • System Trace Macrocell (STM)
  • Trace Memory Controller (TMC)

Customer Successes

Samsung

"Arm CoreSight debug and trace technology was instrumental to the successful bring-up of the Exynos 7870. When designers are working on optimizations to eke out the maximum performance, there is peace of mind in knowing that CoreSight gives the best real-time trace delivering visibility onto the chip fast in order to fine tune the performance" Samsung Exynos 7870

Xilinx

"In addition, Arm CoreSight debug and trace technology was implemented in the chip’s development to provide on-chip visibility that enables fast diagnosis of bugs and performance analysis. Amongst other things, CoreSight ensures it meets the high quality standards required by ISO 26262." Xilinx Zynq-7000


Resources

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Blogs

Community Forums

Suggested answer AXI4 master requirements for unaligned transactions (address v/s WSTRB) 0 votes 99 views 1 replies Latest 12 hours ago by guimers8 Answer this
Not answered TFT/LCD graphic contoller 0 votes 106 views 0 replies Started 16 hours ago by levetop Answer this
Not answered Missing CoreSight components in /renensas/r8a77970.dtsi
  • CoreSight Trace Funnel
  • replicator
  • TPIU
  • AMBA 3 ATB Interface
  • CoreSight System Trace Macrocell (STM)
0 votes 49 views 0 replies Started yesterday by LWT Answer this
Not answered I am working on AXI vip and I am confused about where should I put logic about burst(FIXED,INCR,WRAP) can anybody give me direction ?
  • AXI4
0 votes 66 views 0 replies Started 2 days ago by pure Answer this
Not answered AMBA 5 CHI Coherance protocol details 0 votes 141 views 0 replies Started 5 days ago by JO16 Answer this
Answered Atomic access LDR/STR vs LDREX/STREX
  • AHB-Lite
  • DesignStart
0 votes 666 views 2 replies Latest 6 days ago by EBB Answer this
Suggested answer AXI4 master requirements for unaligned transactions (address v/s WSTRB) Latest 12 hours ago by guimers8 1 replies 99 views
Not answered TFT/LCD graphic contoller Started 16 hours ago by levetop 0 replies 106 views
Not answered Missing CoreSight components in /renensas/r8a77970.dtsi Started yesterday by LWT 0 replies 49 views
Not answered I am working on AXI vip and I am confused about where should I put logic about burst(FIXED,INCR,WRAP) can anybody give me direction ? Started 2 days ago by pure 0 replies 66 views
Not answered AMBA 5 CHI Coherance protocol details Started 5 days ago by JO16 0 replies 141 views
Answered Atomic access LDR/STR vs LDREX/STREX Latest 6 days ago by EBB 2 replies 666 views