CoreLink CCI-500

The Arm CoreLink CCI-500 Cache Coherent Interconnect

Getting Started

The Arm CoreLink CCI-500 Cache Coherent Interconnect extends the performance and low power leadership of Arm mobile systems. It provides full cache coherency between big.LITTLE processor clusters and provides I/O coherency for other agents such as Mali GPU, network interfaces or accelerators. CoreLink CCI-500 offers a scalable and configurable interconnect which enables SoC designers to meet the performance goals with the smallest possible area and power.


Specifications

 Features Details
 AMBA AMBA 4 ACE and ACE-Lite
 ACE slave interfaces 1-4 for fully coherent processors including Arm Cortex
 ACE-Lite slave interfaces 0-6 for IO coherent devices such as Mali processors, accelerators and IO such as PCIe root complex
 Memory and System master interfaces 1-4 memory interfaces
1-2 system interfaces
 Coherency and snoop filter Integrated snoop filter maintains directory of 
processor cache contents, reduces CPU snoops and reduces system power
 Memory map 32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.


  • TRM
  • CoreLink CCI-500 TRM

    For system designers, system integrators and programmers who are designing a SoC, the TRM is the go-to resource.

    CCI-500 TRM
  • A guide on software optimization.
  • AMBA 4 ACE Specification

    CoreLink CCI-500 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency designs.

    AMBA specs
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  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.

    Learn more
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  • System Validation at Arm

    Enabling Partners to Build Better Systems

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  • Introduction to AMBA 4 ACE

    Focused on AMBA ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, Distributed Virtual Memory (DVM) and barrier transaction support. It enables big.LITTLE software to run effectively, increasing system efficiency.

    Download
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  • Quality of Service in Arm Systems

    Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.

    Download
  • A program that is running on a desktop.
  • QoS for Performant and Efficient HD Media.

    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

    Download

Introduction Video

Learn more about CoreLink CCI-500 features, applications and benefits.

Watch video

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Community Blogs

Community Forums

Answered osMutexWait() function before the RTX osKernelInitialize() 0 votes 280 views 9 replies Latest 23 hours ago by Andy Neil Answer this
Answered Code jumps to cxsync1 in vectors.S?
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0 votes 420 views 2 replies Latest yesterday by DanijelDomazet Answer this
Answered Keil uVision compiling with API Issues
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0 votes 207 views 3 replies Latest yesterday by KevinM Answer this
Answered TTBR1_EL2 mmu translation information wrong when E2H=1 0 votes 1149 views 4 replies Latest 2 days ago by lemin9538 Answer this
Answered Breakpoints not working in C code, only in assembly?
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0 votes 899 views 7 replies Latest 2 days ago by Danijel Answer this
Answered Fault Injection in ROM. 0 votes 460 views 6 replies Latest 3 days ago by Broeker Answer this
Answered osMutexWait() function before the RTX osKernelInitialize() Latest 23 hours ago by Andy Neil 9 replies 280 views
Answered Code jumps to cxsync1 in vectors.S? Latest yesterday by DanijelDomazet 2 replies 420 views
Answered Keil uVision compiling with API Issues Latest yesterday by KevinM 3 replies 207 views
Answered TTBR1_EL2 mmu translation information wrong when E2H=1 Latest 2 days ago by lemin9538 4 replies 1149 views
Answered Breakpoints not working in C code, only in assembly? Latest 2 days ago by Danijel 7 replies 899 views
Answered Fault Injection in ROM. Latest 3 days ago by Broeker 6 replies 460 views