The Arm CoreLink CCI-500 Cache Coherent Interconnect extends the performance and low power leadership of Arm mobile systems. It provides full cache coherency between big.LITTLE processor clusters and provides I/O coherency for other agents such as Mali GPU, network interfaces or accelerators. CoreLink CCI-500 offers a scalable and configurable interconnect which enables SoC designers to meet the performance goals with the smallest possible area and power.
|AMBA||AMBA 4 ACE and ACE-Lite|
|ACE slave interfaces||1-4 for fully coherent processors including Arm Cortex|
|ACE-Lite slave interfaces||0-6 for IO coherent devices such as Mali processors, accelerators and IO such as PCIe root complex|
|Memory and System master interfaces||
1-4 memory interfaces
1-2 system interfaces
|Coherency and snoop filter||Integrated snoop filter maintains directory of
processor cache contents, reduces CPU snoops and reduces system power
|Memory map||32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM
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CoreLink CCI-500 TRM
For system designers, system integrators and programmers who are designing a SoC, the TRM is the go-to resource.CCI-500 TRM
AMBA 4 ACE Specification
CoreLink CCI-500 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency designs.AMBA specs
Extended System Coherency
A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.Learn more
System Validation at Arm
Enabling Partners to Build Better SystemsDownload
Introduction to AMBA 4 ACE
Focused on AMBA ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, Distributed Virtual Memory (DVM) and barrier transaction support. It enables big.LITTLE software to run effectively, increasing system efficiency.Download
Quality of Service in Arm Systems
Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.Download
QoS for Performant and Efficient HD Media.
Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.Download
Learn more about CoreLink CCI-500 features, applications and benefits.
Get support with Arm Training courses and design reviews. You can also open a support case or manage existing cases.
|Answered||Disassembly differences||0 votes||485 views||8 replies||Latest 9 hours ago by ludw||Answer this|
|Answered||Keil MDK5 HTTP server - form input names||0 votes||521 views||3 replies||Latest 4 days ago by Murilo Machado||Answer this|
|Answered||Reset process in microcontrollers||0 votes||257 views||1 replies||Latest 5 days ago by Andy Neil||Answer this|
|Answered||Link a pure binary file to image with scatter file||0 votes||1438 views||3 replies||Latest 6 days ago by Ronan Synnott||Answer this|
|Answered||How does AHB-AP access cpu core registers||0 votes||1006 views||2 replies||Latest 7 days ago by Lydia||Answer this|
|Answered||Why does osGetMessageQueue in a thread result in host buffer overflows?||0 votes||905 views||3 replies||Latest 11 days ago by Adam Lins||Answer this|
|Answered||Disassembly differences Latest 9 hours ago by ludw||8 replies 485 views|
|Answered||Keil MDK5 HTTP server - form input names Latest 4 days ago by Murilo Machado||3 replies 521 views|
|Answered||Reset process in microcontrollers Latest 5 days ago by Andy Neil||1 replies 257 views|
|Answered||Link a pure binary file to image with scatter file Latest 6 days ago by Ronan Synnott||3 replies 1438 views|
|Answered||How does AHB-AP access cpu core registers Latest 7 days ago by Lydia||2 replies 1006 views|
|Answered||Why does osGetMessageQueue in a thread result in host buffer overflows? Latest 11 days ago by Adam Lins||3 replies 905 views|