Getting Started

Arm CoreLink Interconnect provides the components and the methodology for designers to build SoCs based on the latest Arm AMBA specifications, maximizing the efficiency of data movement and storage, delivering the performance needed at the lowest power and cost. There are three CoreLink Interconnect families, each optimized for their target applications. High performance SoCs with multiple processor clusters would include a Cache Coherent Interconnect, combined with CoreLink Network Interconnect to provide connectivity for the whole SoC.

Highest Performance Coherency

CoreLink Coherent Mesh Network Chip.

CoreLink Coherent Mesh Network

  • Designed for scaling to the highest performance infrastructure applications including networking and servers.
  • Offering scalable system coherency in multi-core heterogeneous processor systems.
  • Highly configurable and scalable CoreLink CMN-600.
  • Previous generation: CoreLink CCN-512, CCN-508, CCN-504 and CCN-502.
  • Find out more about CMN.
  • Find out more about CCN.

Highest Efficiency Coherency

CoreLink Cache Coherent Interconnects

CoreLink Cache Coherent Interconnect

  • Optimized for the highest efficiency coherent applications including mobile big.LITTLE processing.
  • Offering the smallest and lowest power multi-cluster interconnect.
  • Family consists of: CoreLink CCI-550, CCI-500, CCI-400.
  • Find out more.

Network on Chip (NoC)    

CoreLink Network Interconnect Family

CoreLink Network Interconnect

  • Fully configurable for SoC connectivity across all applications.
  • Hierarchical, low latency and low power connectivity.
  • Back plane for smaller, single processor designs.
  • Companion interconnect for I/O coherency and rest of SoC connectivity with CoreLink CCI and CCN.
  • Family consists of: CoreLink NIC-450, NIC-400 and NIC-301.
  • Find out more.

CoreLink Interconnect Family Comparison

Product CoreLink CMN-600 and
CoreLink CCN Family
CoreLink CCI Family CoreLink NIC Family
Summary Scalable range of high performance, power efficient coherent interconnects targeting network infrastructure and servers.
Configurable interconnect for power and area sensitive applications including mobile big.LITTLE processing, set top box, digital TV, automotive and low cost network infrastructure.
Low latency interconnect for rest of System on Chip (SoC) connectivity, or single cluster processing such as wearables or embedded.
Processors Up to 32 clusters (128 cores) Up to 6 clusters (24 cores) or CPU and GPU coherency Configurable, non-coherent
AMBA Interface AMBA 5 CHI AMBA 4 ACE and AXI4 AMBA 4 AXI4, AXI3, AHB-Lite, APB
Bus Width 128-bit or 256-bit transport
128-bit Configurable 32-bit to 256-bit
Memory Channels 1-8 Channels up to x64-bit 1-6 Channels up to x32-bit
Configurable
I/O Interfaces Up to 96 AXI4 / ACE-Lite interfaces
Up to 0-6 ACE-Lite
Connects multiple devices to CCI and CCN
 

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Answered ARM Cortex M33 Keil Simulator 0 votes 610 views 2 replies Latest 5 days ago by Dicky H Answer this
Answered Weak symbols with GCC and ARMCC
  • MDK-Arm
  • GCC
0 votes 588 views 5 replies Latest 5 days ago by Jure Menart Answer this
Answered Devices missing in pack installer 0 votes 504 views 1 replies Latest 6 days ago by ChenTang Answer this
Answered objcopy.exe -B ARM reports error "objcopy: architecture ARM unknown" in latest versions. 0 votes 492 views 2 replies Latest 6 days ago by Abirami Answer this
Answered CMSIS DSP DCT Type IV or II
  • Digital Signal Processor (DSP)
  • CMSIS
0 votes 229 views 1 replies Latest 9 days ago by Matěj Jirka Answer this
Answered Issues linking the startup file in a precompiled .lib
  • STM32 F1
  • STM32
  • Arm Assembly Language (ASM)
0 votes 1162 views 10 replies Latest 10 days ago by Westonsupermare Pier Answer this
Answered ARM Cortex M33 Keil Simulator Latest 5 days ago by Dicky H 2 replies 610 views
Answered Weak symbols with GCC and ARMCC Latest 5 days ago by Jure Menart 5 replies 588 views
Answered Devices missing in pack installer Latest 6 days ago by ChenTang 1 replies 504 views
Answered objcopy.exe -B ARM reports error "objcopy: architecture ARM unknown" in latest versions. Latest 6 days ago by Abirami 2 replies 492 views
Answered CMSIS DSP DCT Type IV or II Latest 9 days ago by Matěj Jirka 1 replies 229 views
Answered Issues linking the startup file in a precompiled .lib Latest 10 days ago by Westonsupermare Pier 10 replies 1162 views