Getting Started

Arm CoreLink Interconnect provides the components and the methodology for designers to build SoCs based on the latest Arm AMBA specifications, maximizing the efficiency of data movement and storage, delivering the performance needed at the lowest power and cost. There are three CoreLink Interconnect families, each optimized for their target applications. High performance SoCs with multiple processor clusters would include a Cache Coherent Interconnect, combined with CoreLink Network Interconnect to provide connectivity for the whole SoC.

Highest Performance Coherency

CoreLink Coherent Mesh Network Chip.

CoreLink Coherent Mesh Network

  • Designed for scaling to the highest performance infrastructure applications including networking and servers.
  • Offering scalable system coherency in multi-core heterogeneous processor systems.
  • Highly configurable and scalable CoreLink CMN-600.
  • Previous generation: CoreLink CCN-512, CCN-508, CCN-504 and CCN-502.
  • Find out more about CMN.
  • Find out more about CCN.

Highest Efficiency Coherency

CoreLink Cache Coherent Interconnects

CoreLink Cache Coherent Interconnect

  • Optimized for the highest efficiency coherent applications including mobile big.LITTLE processing.
  • Offering the smallest and lowest power multi-cluster interconnect.
  • Family consists of: CoreLink CCI-550, CCI-500, CCI-400.
  • Find out more.

Network on Chip (NoC)    

CoreLink Network Interconnect Family

CoreLink Network Interconnect

  • Fully configurable for SoC connectivity across all applications.
  • Hierarchical, low latency and low power connectivity.
  • Back plane for smaller, single processor designs.
  • Companion interconnect for I/O coherency and rest of SoC connectivity with CoreLink CCI and CCN.
  • Family consists of: CoreLink NIC-450, NIC-400 and NIC-301.
  • Find out more.

CoreLink Interconnect Family Comparison

Product CoreLink CMN-600 and
CoreLink CCN Family
CoreLink CCI Family CoreLink NIC Family
Summary Scalable range of high performance, power efficient coherent interconnects targeting network infrastructure and servers.
Configurable interconnect for power and area sensitive applications including mobile big.LITTLE processing, set top box, digital TV, automotive and low cost network infrastructure.
Low latency interconnect for rest of System on Chip (SoC) connectivity, or single cluster processing such as wearables or embedded.
Processors Up to 32 clusters (128 cores) Up to 6 clusters (24 cores) or CPU and GPU coherency Configurable, non-coherent
AMBA Interface AMBA 5 CHI AMBA 4 ACE and AXI4 AMBA 4 AXI4, AXI3, AHB-Lite, APB
Bus Width 128-bit or 256-bit transport
128-bit Configurable 32-bit to 256-bit
Memory Channels 1-8 Channels up to x64-bit 1-6 Channels up to x32-bit
Configurable
I/O Interfaces Up to 96 AXI4 / ACE-Lite interfaces
Up to 0-6 ACE-Lite
Connects multiple devices to CCI and CCN
 

Learn more CMN
Learn more CCN

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Answered osMutexWait() function before the RTX osKernelInitialize() 0 votes 412 views 9 replies Latest 2 days ago by Andy Neil Answer this
Answered Code jumps to cxsync1 in vectors.S?
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0 votes 639 views 2 replies Latest 2 days ago by DanijelDomazet Answer this
Answered Keil uVision compiling with API Issues
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  • Windows 10
  • api
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0 votes 271 views 3 replies Latest 3 days ago by KevinM Answer this
Answered TTBR1_EL2 mmu translation information wrong when E2H=1 0 votes 1357 views 4 replies Latest 3 days ago by lemin9538 Answer this
Answered Breakpoints not working in C code, only in assembly?
  • Arm Development Studio
0 votes 1114 views 7 replies Latest 3 days ago by Danijel Answer this
Answered Fault Injection in ROM. 0 votes 485 views 6 replies Latest 5 days ago by Broeker Answer this
Answered osMutexWait() function before the RTX osKernelInitialize() Latest 2 days ago by Andy Neil 9 replies 412 views
Answered Code jumps to cxsync1 in vectors.S? Latest 2 days ago by DanijelDomazet 2 replies 639 views
Answered Keil uVision compiling with API Issues Latest 3 days ago by KevinM 3 replies 271 views
Answered TTBR1_EL2 mmu translation information wrong when E2H=1 Latest 3 days ago by lemin9538 4 replies 1357 views
Answered Breakpoints not working in C code, only in assembly? Latest 3 days ago by Danijel 7 replies 1114 views
Answered Fault Injection in ROM. Latest 5 days ago by Broeker 6 replies 485 views