Corstone-300 reference design system
A reference design for building secure SoCs
The Arm Corstone-300 reference design helps you build Secure SoCs quickly – it is the fastest way to incorporate Arm’s most AI-capable Cortex-M processor, the Arm Cortex-M55 processor, into an SoC design.
The Arm Corstone-300 contains various system IP components and a reference design that comprises of processor, security and system IP, as well as software and development tools to help you build secure SoCs quickly. The Corstone-300 has been architected to unlock the performance and power capabilities of the Cortex-M55 processor.
- Provides the fastest way to incorporate the Cortex-M55 processor, with or without the Ethos-U55 processor, into an SoC design.
- Makes chip-level security easier, faster, and more robust with system-wide implementation of TrustZone for Armv8-M.
- Simplifies software development with open-source Trusted Firmware-M (TF-M) for an accelerated route to PSA Certified silicon and devices.
- Design confidently with FPGA and Fixed Virtual Platform (FVP) based on Corstone-300. Choose from well-supported RTOSes, such as RTX, FreeRTOS, Zephyr and Mbed OS to further reduce software development cost.
The following diagram illustrates the Corstone-300 subsystem integration and build.
The Corstone-300 combines software and hardware components for Cortex-M-based designs.
The components include:
Corstone SSE-300 subsystem
The SSE-300 is a reference design based on the Cortex-M55 processor and implements system-level security with TrustZone for Armv8-M. It integrates a single Cortex-M55 processor with External Wakeup Interrupt Controller, AXI interconnect NIC-400-Lite, TrustZone Protection Controllers, Bridges, Access Control Gates, SRAM controllers. It incorporates multiple power domains, clock, and reset control infrastructure. The SSE-300 subsystem is readily extensible and comes with full modification rights. It is everything that you need to kickstart your design and get to market faster.
SIE-300 system IP
All the components that you need to create AMBA AXI systems based on TrustZone for Armv8-M systems: AXI5 memory and peripheral protection controllers, master security controller, bridges, and an optimized SRAM memory controller.
CoreLink SIE-200 System IP
Includes all the components required to create TrustZone-enabled systems. For example, AHB5 interconnect generator, memory and peripheral protection controllers, bridges, and more.
Provides an AMBA AXI5 to AHB5 bridge and an AHB5 to AXI5 bridge.
CoreLink PCK-600 Power Control
The Arm CoreLink PCK-600 Power Control Kit provides a suite of system IP that is pre-verified to ease system power, and clock management infrastructure integration.
CoreLink Generic Flash Controller (GFC-100) enables an embedded Flash macro to be integrated easily into any system.
Similar to GFC-100, but the GFC-200 can have accesses from two masters. The two masters can operate in separate domains, such as a Non-secure domain and a Secure domain.
CoreSight SDC-600 addresses device security needs by allowing silicon and tool vendors to enforce protection and to police debug access, and by working closely with cryptographic elements and debug certificate authentication.
Cortex-M System Design Kit
The Cortex-M System Design Kit (CMSDK) includes many components, such as the multi-layer AHB generator, bridges, adapters, and controllers. The CMSDK offers a reliable and efficient way to connect your system. The CMSDK package includes a few system examples to inspire your future design.
A Real-Time Clock (RTC) for applications that must maintain a time base, which is likely to be the case for all embedded applications.
True Random Number Generator
The True Random Number Generator (TRNG) is the minimum element that you must integrate into a device to ensure a strong security foundation.