Corstone-201 reference design subsystem
Reference design subsystem and system IP for building secure System on Chips
The Arm Corstone-201 offers many flexible reference design subsystems and system IP to help build secure System on Chips (SoCs).
The Arm Corstone-102 combines software and hardware components for Cortex-M-based designs. The highlight of the package is the SSE-200 reference design, it is a subsystem that can be built on or used as a template in a partners design, leading to a faster time to market.
The Corstone-201 combines the following IP:
Corstone SSE-200 subsystem
The SSE-200 reference design subsystem is a fully verified implementation of a dual-core Cortex-M33-based subsystem architecture. Integrating components, for example the interconnects, TrustZone Protection controllers, Bridges, Access Control Gates, instruction caches, SRAM, APB system Peripherals, expansion interfaces, debug, and optional CryptoCell integration. It incorporates multiple power domains, clock, and reset control infrastructure. The SSE-200 subsystem is fully verified, extensible, and comes with full modification rights. The SSE-200 contains everything required to kickstart your design and get to market faster.
Corstone SSE-123 subsystem
The SSE-123 is an example reference design subsystem included in Corstone-201 that provides a secure design for the heart of your Cortex-M23 based system. Designed to be the lowest cost and power efficient implementation of an Arm TrustZone system, it is targeted at the constrained market segment. TrustZone offers an efficient, system-wide approach to security with hardware-enforced isolation built into the CPU.
CoreLink SIE-200 System IP
Includes all the components required to create TrustZone-enabled systems. For example, AHB5 interconnect generator, memory and peripheral protection controllers, bridges, and more.
Corstone SSE-050 subsystem
An efficient and expandable reference design subsystem based on the Cortex-M3 processor.
CoreLink Generic Flash Controller (GFC-100) enables an embedded Flash macro to be integrated easily into any system.
Similar to GFC-100, but the GFC-200 can have accesses from two masters. The two masters can operate in separate domains, such as a Non-secure domain and a Secure domain.
CoreLink PCK-600 Power Control
The Arm CoreLink PCK-600 Power Control Kit provides a suite of system IP that is pre-verified to ease system power, and clock management infrastructure integration.
CoreSight SDC-600 addresses device security needs by allowing silicon and tool vendors to enforce protection and to police debug access, and by working closely with cryptographic elements and debug certificate authentication.
Cortex-M System Design Kit
The Cortex-M System Design Kit (CMSDK) includes many components, such as the multi-layer AHB generator, bridges, adapters, and controllers. The CMSDK offers a reliable and efficient way to connect your system. The CMSDK package includes a few system examples to inspire your future design.
AHB Flash Cache
To get the most of Flash-based systems (either with embedded Flash or external Flash), an efficient cache system is necessary. Within a compact area, this block significantly improves performance and power consumption of your SoC.
A Real-Time Clock (RTC) for applications that must maintain a time base, which is likely to be the case for all embedded applications.
True Random Number Generator
The True Random Number Generator (TRNG) is the minimum element that you must integrate into a device to ensure a strong security foundation.