An essential toolkit for starting SoC design

The Arm Corstone-200 foundation IP complements Arm Cortex-M processors, including the latest Armv8-M generation. It is composed of a subsystem and system IP to help build secure SoCs.

The Corstone-200 foundation IP offers:

  • The fastest secure solution to lead in the IoT market
  • A toolkit to build secure embedded systems
  • A subsystem and configurable system IP package

Features and benefits

The Corstone-200 foundation IP combines software and hardware components for Cortex-M based designs. Components include:

SSE-200 Subsystem - The SSE-200 subsystem is an implementation of a dual core Cortex-M33 based subsystem architecture. Integrating components such as the interconnects, TrustZone protection controllers, bridges, access control gates, instruction caches, SRAM, APB system peripherals, expansion interfaces, debug and optional CryptoCell integration. It also incorporates multiple power domains, clock and reset control infrastructure. The SSE-200 subsystem is fully verified, extensible and comes with full modification rights.

SIE-200 System IP - Includes all the components you need to create TrustZone-enabled systems, such as AHB5 interconnect generator, memory/peripheral protection controllers, bridges and more. 

Corstone SSE-050 Subsystem - An expandable subsystem based on the Arm Cortex-M3 processor for IoT applications.

CMSDK - The Cortex-M System Design Kit (CMSDK) includes many components, such as the multi-layer AHB generator, bridges, adaptors and controllers, offering a reliable and efficient way to connect your system. The CMSDK package includes a few system examples to inspire your future design.

AHB Flash Cache - To get the most of Flash-based systems (either with embedded Flash or external Flash), an efficient cache system is necessary. Within a compact area, this block significantly improves performance and power consumption of your SoC.

RTC - An RTC for applications that need to maintain a time base, which is likely to be the case for all embedded applications.

TRNG - The TRNG is the minimum element that you must integrate into a device to ensure a strong security foundation.

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Answered Inconsistent shareability domain on tlbi instructions
  • Cortex-A72
  • Cortex-A53
0 votes 496 views 3 replies Latest yesterday by josecm Answer this
Answered how to calculate unaligned address for APB? 0 votes 10918 views 8 replies Latest yesterday by Colin Campbell Answer this
Answered What does this message mean? osRtxInfo not found
  • uVision
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Answered Updating my avatar 0 votes 426 views 2 replies Latest 2 days ago by Jerome Decamps - 杜尚杰 Answer this
Answered Problems with setting up the event recorder for LPC1769
  • Cortex-M
  • event
0 votes 943 views 11 replies Latest 2 days ago by coldspark Answer this
Answered Can only step through assembly code and not the C/C++ editor
  • Debugger
0 votes 365 views 4 replies Latest 2 days ago by coldspark Answer this
Answered Inconsistent shareability domain on tlbi instructions Latest yesterday by josecm 3 replies 496 views
Answered how to calculate unaligned address for APB? Latest yesterday by Colin Campbell 8 replies 10918 views
Answered What does this message mean? osRtxInfo not found Latest 2 days ago by Adam Lins 3 replies 430 views
Answered Updating my avatar Latest 2 days ago by Jerome Decamps - 杜尚杰 2 replies 426 views
Answered Problems with setting up the event recorder for LPC1769 Latest 2 days ago by coldspark 11 replies 943 views
Answered Can only step through assembly code and not the C/C++ editor Latest 2 days ago by coldspark 4 replies 365 views