Corstone SSE-700 reference design
This flexible compute subsystem is designed to provide a secure solution for rich IoT applications – ideal for a range of Power, Performance, and Area (PPA) applications. It is powered by the Arm Cortex-A32 processor and includes up to two Cortex-M-based subsystems, providing a standardized programming interface for inter-processor communications. The subsystem implements advanced built-in security features, it is configurable, and allows for the expansion for sensors, connectivity, video, audio, and machine learning on the device.
The Corstone SSE-700 reference design subsystem integrates the following IP:
- Arm Cortex-A32 processor
- Support for integration of up to two external systems, typically Cortex-M based
- Arm CoreLink NIC-450
- Secure Enclave providing root of trust and cryptographic acceleration
- Extensive hardware-based memory protection and error reporting, including Firewall and TrustZone support throughout the system
- A Message Handling Units (MHU) for standardized inter-processor communications
- Advanced and Adaptive Power Management for hardware control of power and clock domains
- System control
- Secure debug interface architecture
The subsystem is aligned with Platform Security Architecture (PSA) principles and it is built for Microsoft Azure Sphere security requirements.