Corstone SSE-200 reference design

The Arm Corstone SSE-200 reference design subsystem integrates the core components of your system in a validated foundation that you can trust.

Building security into an embedded system and integrating all the necessary components take a significant amount of time and effort. The Corstone SSE-200 subsystem aims to make this difficult process easier, by integrating and validating Arm IP in one system.

The Corstone SSE-200 is available as part of Corstone-201.


The Corstone SSE-200 subsystem is based on a two-core structure and integrates features you would expect to find in best-in-class IoT chips.

The Corstone SSE-200 subsystem integrates the following Arm IP:

  • Dual Arm Cortex-M33 processors
  • Arm Corstone SIE-200
  • Instruction caches
  • Arm TrustZone system-level support
  • Power infrastructure components
  • CoreSight SoC

Optional features include:

  • Arm TrustZone CryptoCell

Verified configuration options are also available:

  • Processor configuration and frequencies options
  • RAM sizes and partitioning
  • Cache sizes

Corstone SSE-200 block diagram

Different IoT applications have different requirements, but a very common feature is the need to reduce the power consumption. Reducing power consumption is imperative in IoT designs - if this is ignored, the result could be billions of IoT devices wasting energy.

A dual-core system allows the background OS to run on the energy-efficient core, while the second high-performance processor can be turned on for more demanding tasks. This partitioning delivers significant performance bursts while keeping the average power consumption very low.

Caches have also been integrated in the system to reduce power consuming accesses to the Flash. The always-on domain allows the application to powerdown the system while keeping synchronization.