Arm SecurCore SC300

The Arm SecurCore SC300 processor is designed specifically for high-performance smartcard and embedded security applications. 

Block Diagram on SecurCore SC300.

Getting Started

The SC300 combines the benefits of the industry standard Cortex-M3 processor with the proven security features of Arm SecurCore processors. This enables a high assurance level certification for security-critical applications. Arm SecurCore processors are the most widely licensed 32-bit processors for smartcards worldwide. The programmers’ model is the same as the Cortex-M3. Therefore, the Cortex-M3 documentation listed below can be used for software development. However, explanation of anti-tampering features requires a SecurCore NDA.


Characteristics

Performance efficiency: 3.34 CoreMark/MHz* and 1.25/1.50/1.89 DMIPS/MHz**

   180ULL
(7-track, min 1.8v, 25°C)
 90LP
(7-track, min 1.2v, 25°C)
 40LP
(9-track, min 1.1v, 25°C)
 Dynamic Power

 162 µW/MHz

37 µW/MHz 13 µW/MHz 
 Floorplan area
0.40 mm2
 0.10 mm2  0.028 mm2

** The first result abides by all of the ‘ground rules’ laid out in the Dhrystone documentation. The second result permits inlining of functions, not just the permitted C string libraries. The third result also permits simultaneous (multi-file) compilation. All are with the original (K&R) v2.1 of Dhrystone.

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the SC300 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Forums

Not answered Interrupts not received in secure world for Cortex A7 in Trsuty
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Suggested answer Why don't we see 8+ Cortex A77 cores in a cheap desktop device? Are there driver issues with Linux for such a device? 0 votes 985 views 1 replies Latest yesterday by Zhifei Yang Answer this
Suggested answer Where to start with ARM Trust-zone development for Cortex-A series? 0 votes 1322 views 3 replies Latest yesterday by Zhifei Yang Answer this
Suggested answer Time measurements ARM v8 platform running Linux
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Not answered Cortex-R52 data cache content
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0 votes 67 views 0 replies Started yesterday by Ziv Answer this
Not answered ARM way how to handle and generate own run time error, like try raise catch 0 votes 128 views 0 replies Started 4 days ago by Silicium Answer this
Not answered Interrupts not received in secure world for Cortex A7 in Trsuty Started 14 hours ago by Asmaa 0 replies 72 views
Suggested answer Why don't we see 8+ Cortex A77 cores in a cheap desktop device? Are there driver issues with Linux for such a device? Latest yesterday by Zhifei Yang 1 replies 985 views
Suggested answer Where to start with ARM Trust-zone development for Cortex-A series? Latest yesterday by Zhifei Yang 3 replies 1322 views
Suggested answer Time measurements ARM v8 platform running Linux Latest yesterday by Crystel 3 replies 1287 views
Not answered Cortex-R52 data cache content Started yesterday by Ziv 0 replies 67 views
Not answered ARM way how to handle and generate own run time error, like try raise catch Started 4 days ago by Silicium 0 replies 128 views