Arm SecurCore SC300

The Arm SecurCore SC300 processor is designed specifically for high-performance smartcard and embedded security applications. 

Block Diagram on SecurCore SC300.

Getting Started

The SC300 combines the benefits of the industry standard Cortex-M3 processor with the proven security features of Arm SecurCore processors. This enables a high assurance level certification for security-critical applications. Arm SecurCore processors are the most widely licensed 32-bit processors for smartcards worldwide. The programmers’ model is the same as the Cortex-M3. Therefore, the Cortex-M3 documentation listed below can be used for software development. However, explanation of anti-tampering features requires a SecurCore NDA.


Characteristics

Performance efficiency: 3.34 CoreMark/MHz* and 1.25/1.50/1.89 DMIPS/MHz**

   180ULL
(7-track, min 1.8v, 25°C)
 90LP
(7-track, min 1.2v, 25°C)
 40LP
(9-track, min 1.1v, 25°C)
 Dynamic Power

 162 µW/MHz

37 µW/MHz 13 µW/MHz 
 Floorplan area
0.40 mm2
 0.10 mm2  0.028 mm2

** The first result abides by all of the ‘ground rules’ laid out in the Dhrystone documentation. The second result permits inlining of functions, not just the permitted C string libraries. The third result also permits simultaneous (multi-file) compilation. All are with the original (K&R) v2.1 of Dhrystone.

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the SC300 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Forums

Not answered initialisation of DRAM ECC with Cortex A9 CPU 0 votes 10 views 0 replies Started 5 hours ago by flongnos Answer this
Suggested answer FVP MPS2 UART memory map 0 votes 285 views 2 replies Latest 9 hours ago by Gabor M. Answer this
Suggested answer Cortex A9 MMU 0 votes 1430 views 7 replies Latest 20 hours ago by flongnos Answer this
Suggested answer Does the processor frequency change when switching from secure to non secure domain?
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Suggested answer Is there any way to enforce padding between subroutines using the scatter file?
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0 votes 265 views 8 replies Latest yesterday by Ghantaz Answer this
Suggested answer A low-overhead real time counter consistent cross processor cores 0 votes 8636 views 1 replies Latest yesterday by Zhifei Yang Answer this
Not answered initialisation of DRAM ECC with Cortex A9 CPU Started 5 hours ago by flongnos 0 replies 10 views
Suggested answer FVP MPS2 UART memory map Latest 9 hours ago by Gabor M. 2 replies 285 views
Suggested answer Cortex A9 MMU Latest 20 hours ago by flongnos 7 replies 1430 views
Suggested answer Does the processor frequency change when switching from secure to non secure domain? Latest yesterday by Ghantaz 2 replies 224 views
Suggested answer Is there any way to enforce padding between subroutines using the scatter file? Latest yesterday by Ghantaz 8 replies 265 views
Suggested answer A low-overhead real time counter consistent cross processor cores Latest yesterday by Zhifei Yang 1 replies 8636 views