SecurCore SC000

The Arm SecurCore SC000 processor is designed specifically for the highest-volume smartcard and embedded security applications. 

Getting Started

The SC000 combines the low power and low area from the Cortex-M0 processor with the proven security features of Arm SecurCore processors. This enables a high assurance level certification for security-critical applications. Arm SecurCore processors are the most widely licensed 32-bit processors for smartcards worldwide. The programmers’ model is the same as the Cortex-M0. Therefore, the Cortex-M0 documentation listed below can be used for software development. However, explanation of anti-tampering features requires a SecurCore NDA.


Characteristics

Performance efficiency: 2.33 CoreMark/MHz* and 0.87/1.02/1.27 DMIPS/MHz**

   180ULL
(7-track, min 1.8v, 25°C)
 90LP
(7-track, min 1.2v, 25°C)
 40LP
(9-track, min 1.1v, 25°C)
 Dynamic Power
74 µW/MHz 11.2 µW/MHz 4.6µW/MHz
 Floorplan area
0.125 mm2
0.034 mm2 0.008 mm2

** The first result abides by all of the ‘ground rules’ laid out in the Dhrystone documentation. The second result permits inlining of functions, not just the permitted C string libraries. The third result also permits simultaneous (multi-file) compilation. All are with the original (K&R) v2.1 of Dhrystone.

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the SC000 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Blogs

Community Forums

Answered Inconsistent shareability domain on tlbi instructions
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0 votes 496 views 3 replies Latest yesterday by josecm Answer this
Not answered Memory violation calling ATSAM3X8 0 votes 156 views 0 replies Started yesterday by ccandido Answer this
Suggested answer Instruction Count and Memory Access
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0 votes 962 views 7 replies Latest 2 days ago by 42Bastian Schick Answer this
Suggested answer PSA Certified Devices
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0 votes 500 views 1 replies Latest 3 days ago by adrianlshaw Answer this
Not answered SWD: Cannot connect to MEM-AP on Cortex-M0 Designstart Eval
  • Cortex-M0
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  • SWD
0 votes 77 views 0 replies Started 3 days ago by Bernhard Lang Answer this
Answered Inconsistent shareability domain on tlbi instructions Latest yesterday by josecm 3 replies 496 views
Not answered Memory violation calling ATSAM3X8 Started yesterday by ccandido 0 replies 156 views
Suggested answer Instruction Count and Memory Access Latest 2 days ago by Lica 2 replies 260 views
Suggested answer Understanding interrupt latency and jitter in Cortex-M Latest 2 days ago by 42Bastian Schick 7 replies 962 views
Suggested answer PSA Certified Devices Latest 3 days ago by adrianlshaw 1 replies 500 views
Not answered SWD: Cannot connect to MEM-AP on Cortex-M0 Designstart Eval Started 3 days ago by Bernhard Lang 0 replies 77 views