SecurCore

Arm SecurCore processors are designed specifically for high-performance and high-volume smartcard and embedded security applications. 

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Not answered making physical memory pages not cacheable (probabaly by modifying page table entry) 0 votes 44 views 0 replies Started 12 hours ago by Gol Answer this
Suggested answer Debug Connection Cause ExecutionTiming Problem on Second Core of Cortex A9 on Zynq 702 MPCore
  • System on Chip (SoC)
  • Cortex-A9
0 votes 1360 views 3 replies Latest 12 hours ago by BurakSeker Answer this
Not answered PendSV target secure state 0 votes 48 views 0 replies Started yesterday by Jiameng Answer this
Suggested answer Processor halt in __libc_init_array assembler function 0 votes 1265 views 6 replies Latest yesterday by lammers7 Answer this
Suggested answer flush_cache_all() API consuming 200+ microseconds. 0 votes 919 views 5 replies Latest 3 days ago by vaiyawa Answer this
Suggested answer R5 vs A9 Performances
  • Cortex-A9
  • Cortex-R5
0 votes 1531 views 9 replies Latest 3 days ago by Poz1 Answer this
Not answered making physical memory pages not cacheable (probabaly by modifying page table entry) Started 12 hours ago by Gol 0 replies 44 views
Suggested answer Debug Connection Cause ExecutionTiming Problem on Second Core of Cortex A9 on Zynq 702 MPCore Latest 12 hours ago by BurakSeker 3 replies 1360 views
Not answered PendSV target secure state Started yesterday by Jiameng 0 replies 48 views
Suggested answer Processor halt in __libc_init_array assembler function Latest yesterday by lammers7 6 replies 1265 views
Suggested answer flush_cache_all() API consuming 200+ microseconds. Latest 3 days ago by vaiyawa 5 replies 919 views
Suggested answer R5 vs A9 Performances Latest 3 days ago by Poz1 9 replies 1531 views