SecurCore

Arm SecurCore processors are designed specifically for high-performance and high-volume smartcard and embedded security applications. 

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Answered Non-secure configuration of UART1 on Arm Musca-A1
  • Musca-A
  • TrustZone for Armv8-M
0 votes 226 views 4 replies Latest 9 hours ago by Daniel Oliveira Answer this
Not answered Timer interrupts synchronization in Cortex M4
  • Cortex-M4
  • Interrupt
0 votes 37 views 0 replies Started 9 hours ago by satheesh21 Answer this
Not answered Arm64 Long Format Translation Table Walk
  • Armv8-A
  • Memory Management Unit (MMU)
0 votes 97 views 0 replies Started 13 hours ago by angeld Answer this
Suggested answer How long does it take for Cortex A53 to exit low power state? 0 votes 333 views 2 replies Latest 14 hours ago by Andy Neil Answer this
Suggested answer Optimization of Neon Intrinsics on ARM cortexa53
  • Cortex-A53
  • AArch64
  • Optimization Solution
  • GCC
  • NEON
  • Arm Assembly Language (ASM)
0 votes 716 views 12 replies Latest 17 hours ago by 42Bastian Schick Answer this
Answered timestamp generator register location on Cortex-M4 (PSELCTRL CNTCR)
  • CoreSight Architecture
  • Cortex-M
  • Debugging
  • CoreSight
  • Cortex-M4
0 votes 317 views 1 replies Latest 19 hours ago by 42Bastian Schick Answer this
Answered Non-secure configuration of UART1 on Arm Musca-A1 Latest 9 hours ago by Daniel Oliveira 4 replies 226 views
Not answered Timer interrupts synchronization in Cortex M4 Started 9 hours ago by satheesh21 0 replies 37 views
Not answered Arm64 Long Format Translation Table Walk Started 13 hours ago by angeld 0 replies 97 views
Suggested answer How long does it take for Cortex A53 to exit low power state? Latest 14 hours ago by Andy Neil 2 replies 333 views
Suggested answer Optimization of Neon Intrinsics on ARM cortexa53 Latest 17 hours ago by 42Bastian Schick 12 replies 716 views
Answered timestamp generator register location on Cortex-M4 (PSELCTRL CNTCR) Latest 19 hours ago by 42Bastian Schick 1 replies 317 views