Neoverse N1

Accelerating the transformation to a scalable cloud-to-edge infrastructure.

Neoverse N1 block diagram

Getting Started

The Arm Neoverse N1 CPU combines server-class features and thread performance with cutting -edge low power design techniques delivering revolutionary performance per watt for building the next-generation cloud-to-edge infrastructure. By co-optimizing the N1 CPU with the CMN-600 coherent mesh interconnect that supports chip-to-chip connectivity over CCIX, the N1 platform allows extreme scalability from 8 to16 cores/chip for networking, storage, security and edge compute nodes, to 128+ cores/socket in hyperscale servers. Built on a common Armv8.2-A software foundation with the Neoverse E1 CPU, seamless heterogeneous systems can be realized encompassing accelerated functions for infrastructure deployments in 5G, data analytics, and smart networking. Integrated with Arm’s Ethos processor, the N1 CPU can deliver a self-hosted inference accelerator for AI/ML applications.

Key Features

  • 30% more performance/watt than Cortex-A72 on the same technology node
  • Large 1MB private L2 cache with up to 128MB system level cache in the mesh interconnect
  • Low-latency direct-connect interface between the CPU and mesh interconnect
  • I-cache coherency to enable a broader range of server workloads
  • Microarchitecture for large footprint, branch-heavy workloads
  • Double the vector and crypto compute bandwidth over previous generation
  • Manageable, full-frequency, sustainable performance without compromising compute efficiency
  • Server-class virtualization, RAS and code profiling

Specifications

Architecture Armv8-A (Harvard)
Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Cryptography extensions
  • RAS extensions
  • SPE extensions
  • Armv8.3 LDAPR instructions
  • Armv8.4 Dot Product instructions
  • Armv8.5 (security vulnerabilities mitigations)
ISA support
  • A64
  • A32 and T32 (at the EL0 only)
Microarchitecture Pipeline Out-of-order
Superscalar  Yes
Neon/Floating Point Unit  Included 
Cryptography Unit  Optional 
Max number of CPUs in cluster  Four (4) or direct-connect
Physical addressing (PA)  48-bit 
Memory system and external interfaces L1 I-Cache/D-Cache 64kB
L2 Cache 1MB to 512kB, or 256kB
L3 Cache  Optional, 512kB TO 4MB 
ECC Support  Yes 
LPAE  Yes
Bus interfaces  AMBA CHI or ACE
ACP  Optional with cluster
Peripheral Port Optional with cluster
Other Security  TrustZone
Interrupts  GIC interface, GICv34 
Generic timer  Armv8-A 
PMU  PMUv3
Debug  Armv8-A (plus Armv8.2-A extensions) 
CoreSight  CoreSightv3 
Embedded Trace Macrocell ETMv4.2 (instruction trace)

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Community Forums

Not answered Where do I find presentations and photos from SC'18? 2 votes 4554 views 0 replies Started 1 years ago by John Linford Answer this
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Suggested answer STM32, Keil + first steps in astrology?
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Suggested answer I2C problem on Cypress PSoC3 (with EEPROM and FRAM too) 0 votes 5143 views 5 replies Latest 8 hours ago by Andy Neil Answer this
Suggested answer FVP MPS2 UART memory map 0 votes 287 views 2 replies Latest 10 hours ago by Gabor M. Answer this
Not answered Where do I find presentations and photos from SC'18? Started 1 years ago by John Linford 0 replies 4554 views
Not answered initialisation of DRAM ECC with Cortex A9 CPU Started 6 hours ago by flongnos 0 replies 17 views
Not answered Creating an Assembly project in DS IDE 2020 Started 8 hours ago by Brittany_ruth 0 replies 83 views
Suggested answer STM32, Keil + first steps in astrology? Latest 8 hours ago by Andy Neil 3 replies 234 views
Suggested answer I2C problem on Cypress PSoC3 (with EEPROM and FRAM too) Latest 8 hours ago by Andy Neil 5 replies 5143 views
Suggested answer FVP MPS2 UART memory map Latest 10 hours ago by Gabor M. 2 replies 287 views