Neoverse E1

The Neoverse E1 processor is a new class of highly efficient CPU designed specifically for throughput compute workloads.

Neoverse E1 block diagram

Getting started

The Arm Neoverse E1 CPU delivers best in class throughput efficiency. It incorporates a new simultaneous multithreading (SMT) microarchitecture design. With SMT, the processor can execute two threads concurrently resulting in better aggregate throughput performance.

The Neoverse E1 delivers 2.1x more compute performance, 2.7x more throughput performance and 2.4x better throughput efficiency compared to the Cortex-A53. The design is highly scalable to support throughput demands for next generation edge to core data transport.


Specifications

General Architecture Armv8-A (Harvard)
Extensions
  • Armv8.1 extensions
  • Armv8.2 extensions
  • Advanced SIMD and floating-point
  • Cryptography extensions
  • RAS extensions
  • Armv8.3 LDAPR instructions
  • Armv8.4 Dot Product support instructions
  • Armv8.5 PSTATE SSBS bit
  ISA support A64
Microarchitecture Pipeline Out-of-order
Superscalar Yes
Neon and Floating Point Unit Included
Cryptography Unit Optional
Max number of CPUs in cluster Eight (8)
  Physical addressing (PA) 44-bit
Memory system and external interfaces L1 I-Cache and D-Cache 32KB to 64KB
  L2 Cache Optional, 64KB to 256KB
  L3 Cache Optional, 512KB to 4MB
  ECC Support Yes
  Bus interfaces AMBA ACE or CHI
  ACP Optional
  Peripheral Port Optional
Other Functional Safety Support Safety package
Security TrustZone
  Interrupts GIC interface, GICv4
  Generic timer Armv8-A
  PMU PMUv3
  Debug Armv8-A (plus Armv8.2-A extensions)
  CoreSight CoreSightv3
  Embedded Trace Macrocell ETMv4.2 (instruction trace)

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Answered Inconsistent shareability domain on tlbi instructions
  • Cortex-A72
  • Cortex-A53
0 votes 496 views 3 replies Latest yesterday by josecm Answer this
Answered how to calculate unaligned address for APB? 0 votes 10925 views 8 replies Latest yesterday by Colin Campbell Answer this
Answered What does this message mean? osRtxInfo not found
  • uVision
0 votes 430 views 3 replies Latest 2 days ago by Adam Lins Answer this
Answered Updating my avatar 0 votes 427 views 2 replies Latest 2 days ago by Jerome Decamps - 杜尚杰 Answer this
Answered Problems with setting up the event recorder for LPC1769
  • Cortex-M
  • event
0 votes 945 views 11 replies Latest 2 days ago by coldspark Answer this
Answered Can only step through assembly code and not the C/C++ editor
  • Debugger
0 votes 366 views 4 replies Latest 2 days ago by coldspark Answer this
Answered Inconsistent shareability domain on tlbi instructions Latest yesterday by josecm 3 replies 496 views
Answered how to calculate unaligned address for APB? Latest yesterday by Colin Campbell 8 replies 10925 views
Answered What does this message mean? osRtxInfo not found Latest 2 days ago by Adam Lins 3 replies 430 views
Answered Updating my avatar Latest 2 days ago by Jerome Decamps - 杜尚杰 2 replies 427 views
Answered Problems with setting up the event recorder for LPC1769 Latest 2 days ago by coldspark 11 replies 945 views
Answered Can only step through assembly code and not the C/C++ editor Latest 2 days ago by coldspark 4 replies 366 views