Cortex-M35P

A Cortex-M processor with physical security features and optional software isolation using TrustZone for Armv8-M.

Cortex-M35P Block Diagram

Getting Started

For embedded developers seeking to hinder physical tampering and achieve a higher level of security certification, Arm offers the Cortex-M35P: a robust, high-performing processor. It builds upon the proven Arm Cortex-M technology deployed in billions of SoCs, making physical and software security accessible for all developers. 

Cortex-M35P with physical security features, memory protection, and TrustZone security for hardware-enforced isolation is certified to EAL6+ for the Common Criteria ISO 15408 standard, one of the most stringent security evaluation methodologies. This certification helps SoC designers develop products with as much security assurance as possible.

Specifications

Architecture Armv8-M with Mainline extension
Bus Interface  2x AMBA5 AHB (Harvard bus architecture)
ISA Support Thumb/Thumb-2
Pipeline Three-stage
Software Security Optional TrustZone for Armv8-M, with optional Security Attribution Unit of up to 8 regions
Stack limit checking
Physical Security Built-in protection from invasive and non-invasive attacks
DSP Extensions Optional DSP/SIMD instructions Single cycle 16/32-bit MAC Single cycle dual 16-bit MAC 8/16-bit SIMD arithmetic
Floating Point Unit Optional single precision floating point unit IEEE 754 compliant
Co-processor Interface Optional dedicated co-processor bus interface for up to 8 co-processor units for custom compute
Memory Protection Optional Memory Protection Unit (MPU) with up to 16 regions per security state
Interrupts Non-Maskable Interrupt (NMI) and up to 480 physical interrupts with 8 to 256 priority levels
Wake-up Interrupt Controller Optional for waking up the processor from state retention power gating or when all clocks are stopped
Sleep Modes Integrated Wait for Event (WFE) and Wait for Interrupt (WFI) instructions with Sleep On Exit functionality
Debug Optional JTAG and Serial Wire Debug ports. Up to 8 Breakpoints and 4 Watchpoints
Trace Optional Instruction Trace (ETM), Micro Trace Buffer (MTB), Data Trace (DWT), and Instrumentation Trace (ITM)
Cache Instruction cache
Dual Core Lock-Step Support (DCLS)
Yes, DCLS configuration

Compare all Cortex-M processors

Characteristics

Performance efficiency 4.02 CoreMark/MHz* and 1.50 DMIPS/MHz**

 Arm Cortex-M35P Implementation Data***
  40LP
(7-track, typical 0.99V, -40°C) 
28HT
(7-track, typical 0.81V, 0°C) 
 16FFC
(9-track, typical 0.72V, 0°C)
Dynamic Power 
14.7 μW/MHz   9.2 μW/MHz   5.1 μW/MHz 
Floor Planned Area
0.091 mm2
 0.034 mm2  0.021 mm2

*Arm Compiler 6.12 Flags Cortex-M35P --fpu=FPv5-SP.

**The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone.

***Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU, FPU, DSP and debug.


  • Manual containing technical information.
  • Physical Security White Paper

    This white paper explains the importance of physical security and solutions for mitigation, taking a closer look at the Arm Cortex-M35P.

    Read here
  • A program that is running on a desktop.
  • Armv8-M Architecture - Technical Overview and Reference Manual

    Access Armv8-M documentation including the reference manual and an introduction to TrustZone technology.


    Read here
  • a ulink, a board, a desktop.
  • Software Development Tools for Cortex-M series

    Arm and its ecosystem partners provide a range of tools, software frameworks, operating systems and platforms for Cortex-M processors.

    Read here
  • A locking device.
  • TrustZone for Armv8-M

    Arm TrustZone technology provides system-wide hardware isolation for trusted software. Learn how to implement TrustZone on Armv8-M processors.

    Read here
  • A guide on software optimization.
  • DSP Extension

    DSP extension to the Thumb instruction set improves the performance of numerical algorithms. They provide the opportunity to perform signal processing operations directly on the Cortex-M35P.

    Read here
  • Systems supporting the main system.
  • Corstone Foundation IP

    Speed up your SoC Design with Corstone subsystem, a pre-verified, configurable and modifiable subsystem that pre-integrates Cortex-M processor and security IP with the most relevant system components.

    Read here

Cortex-M comparison table
Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M55
Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv8.1-M Mainline
Helium
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.98 1.25-1.89  1.25-1.95  1.5  1.5   1.6 2.14-3.23
CoreMark®/MHz*
2.33 2.46  1.85
2.64 3.34 3.42  4.02 4.02  4.2 5.01
Pipeline Stages
 4
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) (2 x)
Yes (option) 
Maximum MPU Regions  16  16  16  16
16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
ETMv4 (option)
Digital Signal Processing (DSP) extension
No  No  No  No  No Yes  Yes (option) Yes (option)  Yes (option)
Yes 
Floating Point Hardware  No No  No  No  No Yes (scalar SP) Yes (scalar SP) Yes (scalar SP) Yes (scalar HP +
SP + DP) (vector
HP + SP)
Yes (scalar SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes (2 x)
Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option)
Yes (option 4-64kB 
 I-cache I-cache and D-cache
I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM)
Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  Yes (option)
No 
Coprocessor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  Yes (option)
No 
Bus Protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI5 (main bus), AHB
(peripheral bus,
TCM slave port and debug)
AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes
Yes 
Integrated Interrupt Controller (NVIC)
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes  Yes 
Maximum # External Interrupts
32  32  32  240  240  240  480 480 480
240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes
Yes 
Single Cycle Multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes
Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes
Yes 
Dual Core Lock-Step Support
No No No Yes  No No Yes Yes  No
Yes 
Arm Custom Instructions
No
No
No
No
No
No
Yes
No
Yes (available in 2021)
No
Common Criteria certification No No  No  No  No  No  Yes  Yes  No No 

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

HP = Half Precision


Related IP and tools

The Cortex-M35P processor can be incorporated into an SoC using a broad range of Arm technology, including System IP and Physical IP. It is fully supported by development tools from Arm and the Arm ecosystem. Related IP includes:

Related IP Tools  Software
SCA mitigation IP Arm Development Studio Cortex Microcontroller Software Interface Standard
IoT SoC solutions Arm Compiler Pelion IoT Platform
TrustZone CryptoIsland and CryptoCell Cortex-M Prototyping System Mbed OS
Corstone Foundation IP Fast Models Trusted Firmware-M
Direct Memory Access Controller    

Get Support

Community Forums

Suggested answer Cortex A9 MMU 0 votes 1810 views 10 replies Latest 12 hours ago by deas Answer this
Suggested answer initialisation of DRAM ECC with Cortex A9 CPU 0 votes 378 views 3 replies Latest yesterday by 42Bastian Schick Answer this
Suggested answer FVP MPS2 UART memory map 0 votes 334 views 2 replies Latest yesterday by Gabor M. Answer this
Suggested answer Does the processor frequency change when switching from secure to non secure domain?
  • Cortex-M23
  • TrustZone for Armv8-M
0 votes 274 views 2 replies Latest 2 days ago by Ghantaz Answer this
Suggested answer Is there any way to enforce padding between subroutines using the scatter file?
  • Cortex-M23
  • Arm Assembly Language (ASM)
0 votes 357 views 8 replies Latest 2 days ago by Ghantaz Answer this
Suggested answer A low-overhead real time counter consistent cross processor cores 0 votes 8891 views 1 replies Latest 2 days ago by Zhifei Yang Answer this
Suggested answer Cortex A9 MMU Latest 12 hours ago by deas 10 replies 1810 views
Suggested answer initialisation of DRAM ECC with Cortex A9 CPU Latest yesterday by 42Bastian Schick 3 replies 378 views
Suggested answer FVP MPS2 UART memory map Latest yesterday by Gabor M. 2 replies 334 views
Suggested answer Does the processor frequency change when switching from secure to non secure domain? Latest 2 days ago by Ghantaz 2 replies 274 views
Suggested answer Is there any way to enforce padding between subroutines using the scatter file? Latest 2 days ago by Ghantaz 8 replies 357 views
Suggested answer A low-overhead real time counter consistent cross processor cores Latest 2 days ago by Zhifei Yang 1 replies 8891 views