Specifications

The Cortex-M23 processor is a very compact, two-stage pipelined processor that supports the Armv8-M baseline instruction set. The Cortex-M23 with TrustZone is the ideal processor for the most constrained IoT and embedded applications where security is a key requirement. 

TrustZone for Armv8-M provides hardware-enforced isolation between the trusted and the untrusted resources on the Cortex-M23 device, while maintaining the efficient exception handling and determinism that have been the hallmark of all Cortex-M processors. 

Block Diagram on Cortex-M23.
Architecture Armv8-M Baseline 
Bus Interface AMBA 5 AHB (Von Neumann bus architecture)
Optional single cycle I/O interface
ISA Support Thumb/Thumb-2 subset
Pipeline Two-stage
Software Security Optional TrustZone for Armv8-M with optional security
Attribution Unit of up to 8 regions
Stack limit checking for Secure stack pointers
Memory Protection Optional Memory Protection Unit (MPU) with up to 16 regions per security state
Interrupts Non-maskable Interrupt (NMI) and up to 240 physical interrupts with 4 priority levels
Wake-up Interrupt Controller Optional for waking up the processor from state retention power gating or when all clocks are stopped
Sleep Modes Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep and Deep Sleep Signals
Enhanced Instructions Hardware single-cycle (32x32) multiply and fast (32/32) divide option
Debug Optional JTAG or Serial Wire Debug ports, up to 4 Breakpoints and 4 Watchpoints
Trace Optional Micro Trace Buffer (MTB) or Embedded Trace Macrocell (ETM)

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you are ready to manufacture.

Learn more

Characteristics

Performance efficiency 2.64 CoreMark/MHz* and 0.98 DMIPS/MHz**

Arm Cortex-M23 Implementation Data***
  40LP
(9-track, typical 0.99V,-40°C)
28HPC+
(9-track, typical 0.81V, 0°C)
Dynamic power 3.86 μW/MHz
2.26 μW/MHz
Floor planned area
0.0088 mm2
0.0037 mm2

*See: EEMBC Benchmark Score Viewer

**The result abides by all of the “ground rules” laid out in the Dhrystone documentation and using the original (K&R) v2.1 of Dhrystone.

*** Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU and debug.


Cortex-M comparison table

Download the following PDF datasheet to compare the specifications of Cortex-M processors.

Download