Cortex-M1

The first Arm processor designed specifically for implementation in FPGAs. 

Getting Started

The Cortex-M1 processor targets FPGA devices and includes support for leading FPGA synthesis tools, allowing the designer to choose the optimal implementation for each project.

The Cortex-M1 processor enables OEMs to achieve significant cost savings through rationalization of software and tools investments across multiple projects spanning FPGA, ASIC and ASSP, plus greater vendor independence through use of an industry-standard processor.

Arm DesignStart FPGA provides instant and free access to Cortex-M1 soft CPU IP for use on FPGA designs for prototypes and commercial deployments.

Learn more about DesignStart.

Arm Cortex-M1 chip diagram

Specifications

Architecture Armv6-M
Bus Interface AMBA  AHB-Lite, Von Neumann Bus Architecture with optional Tightly Coupled Memory interfaces (I-TCM and D-TCM)
ISA Support Thumb/Thumb-2 subset
Pipeline Three-stage
SysTick Timer Optional
Multiplier Options of fast or area optimized 32-x32 multiplier
Bit Manipulation Bit banding region can be implemented with Corstone Foundation IP
Interrupts Non-maskable interrupt (NMI) +1 to 32 interrupts (configurable)
Wakeup Interrupt Controller None
Interrupt Priority Levels 4 priority levels per interrupt
Instruction and Data Tightly Coupled Memories 0K - 1024K (configurable)
Debug Full or reduced debug (full - 4 breakpoint comparators, 2 watchpoint comparators)

Compare all Cortex-M processors

Characteristics

Performance Efficiency: 1.85 CoreMark/MHz* and 0.8 DMIPS/MHz

  • Manual containing technical information.
  • Cortex-M1 Technical Reference Manual

    For system designers, integrators and testers, the Technical Reference Manual (TRM) provides details of the Cortex-M1 processor.

    Read here
  • Papers filed, in a formal order.
  • Armv6-M Architecture Reference Manual

    This manual describes the instruction set, memory model, and programmers' model for Armv6-M compliant processors. 


    Read here
  • Tools and durable equipment.
  • Cortex-M1 FPGA Development Kit - GOWIN

    For FPGA system designers and programmers who want to incorporate and program the Cortex-M1 processor in a GOWIN-based FPGA design.

    Read here
  • a ulink, a board, a desktop.
  • Software Development Tools for Cortex-M

    Arm and its ecosystem partners provide a range of tools, software frameworks, operating systems and platforms for Cortex-M processors.

    Read here
  • Tools and durable equipment.
  • Cortex-M1 FPGA Development Kit - Xilinx

    For FPGA system designers and programmers who want to incorporate and program the Cortex-M1 processor in an Xilinx-based FPGA design

    Read here
  • Line drawing of letter, email etc.
  • Cortex-M Resources

    List of useful links and resources for developers designing with Cortex-M processors.

    Read here
Cortex-M comparison table
Feature  Cortex-M0 Cortex-M0+ Cortex-M1 Cortex-M23 Cortex-M3 Cortex-M4  Cortex-M33 Cortex-M35P  Cortex-M55
Cortex-M7 
Instruction Set Architecture  Armv6-M Armv6-M
Armv6-M
Armv8-M Baseline 
Armv7-M Armv7-M
Armv8-M Mainline
Armv8-M Mainline
Armv8.1-M Mainline
Helium
Armv7-M
Thumb, Thumb-2  Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb, Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
Thumb,
Thumb-2
DMIPS/MHz range*
0.87-1.27  0.95-1.36  0.8
0.98 1.25-1.89  1.25-1.95  1.5  1.5   1.6 2.14-3.23
CoreMark®/MHz*
2.33 2.46  1.85
2.64 3.34 3.42  4.02 4.02  4.2 5.01
Pipeline Stages
 4
Memory Protection Unit (MPU)  No  Yes (option) No  Yes (option)
(2 x) 
Yes (option)  Yes (option)  Yes (option)
(2 x) 
Yes (option)
(2 x) 
Yes (option) (2 x)
Yes (option) 
Maximum MPU Regions  16  16  16  16
16 
Trace (ETM or MTB)  No  MTB (option)  No  MTB (option) or 
ETMv3 (option) 
ETMv3 (option)  ETMv3 (option)  MTB (option) and/or
ETMv4 (option) 
MTB (option) and/or
ETMv4 (option) 
ETMv4 (option)
ETMv4 (option)
Digital Signal Processing (DSP) extension
No  No  No  No  No Yes  Yes (option) Yes (option)  Yes (option)
Yes 
Floating Point Hardware  No No  No  No  No Yes (scalar SP) Yes (scalar SP) Yes (scalar SP) Yes (scalar HP +
SP + DP) (vector
HP + SP)
Yes (scalar SP + DP) 
Systick Timer
Yes (option)  Yes (option)  Yes (option)  Yes (2 x)  Yes Yes Yes (2 x) Yes (2 x) Yes (2 x)
Yes
Built-in Caches  No No No  No No No No  Yes (option 2- 16kB Yes (option)
Yes (option 4-64kB 
 I-cache I-cache and D-cache
I-cache, D-cache) 
Tightly Coupled Memory  No  No  Yes  No  No  No  No  No  Yes
(option 0-16MB
I-TCM/D-TCM)
Yes
(option 0-16MB
I-TCM/D-TCM) 
TrustZone for Armv8-M
No No No Yes (option)  No  No  Yes (option) Yes (option)  Yes (option)
No 
Coprocessor Interface  No  No  No  No  No  No  Yes (option)  Yes (option)  Yes (option)
No 
Bus Protocol
AHB Lite  AHB Lite, Fast I/O  AHB Lite  AHB5, Fast I/O  AHB Lite, APB   AHB Lite, APB  AHB5, APB AHB5, APB AXI5 (main bus), AHB
(peripheral bus,
TCM slave port and debug)
AXI4, AHB Lite, APB, TCM
Wake-up Interrupt Controller Support
Yes Yes  No  Yes  Yes  Yes  Yes  Yes  Yes
Yes 
Integrated Interrupt Controller (NVIC)
Yes  Yes  Yes  Yes  Yes  Yes  Yes Yes  Yes  Yes 
Maximum # External Interrupts
32  32  32  240  240  240  480 480 480
240  
Hardware Divide  No No  No  Yes  Yes  Yes  Yes  Yes Yes
Yes 
Single Cycle Multiply
Yes (option) Yes (option)  No  Yes  Yes  Yes  Yes  Yes  Yes
Yes 
CMSIS Support
Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes  Yes
Yes 
Dual Core Lock-Step Support
No No No Yes  No No Yes Yes  No
Yes 
Arm Custom Instructions
No
No
No
No
No
No
Yes
No
Yes (available in 2021)
No
Common Criteria certification No No  No  No  No  No  Yes  Yes  No No 

*See individual Cortex-M product pages for further information.

SP = Single Precision

DP = Double Precision

HP = Half Precision


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Not answered initialisation of DRAM ECC with Cortex A9 CPU 0 votes 10 views 0 replies Started 5 hours ago by flongnos Answer this
Suggested answer FVP MPS2 UART memory map 0 votes 285 views 2 replies Latest 9 hours ago by Gabor M. Answer this
Suggested answer Cortex A9 MMU 0 votes 1430 views 7 replies Latest 20 hours ago by flongnos Answer this
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Suggested answer A low-overhead real time counter consistent cross processor cores 0 votes 8636 views 1 replies Latest yesterday by Zhifei Yang Answer this
Not answered initialisation of DRAM ECC with Cortex A9 CPU Started 5 hours ago by flongnos 0 replies 10 views
Suggested answer FVP MPS2 UART memory map Latest 9 hours ago by Gabor M. 2 replies 285 views
Suggested answer Cortex A9 MMU Latest 20 hours ago by flongnos 7 replies 1430 views
Suggested answer Does the processor frequency change when switching from secure to non secure domain? Latest yesterday by Ghantaz 2 replies 224 views
Suggested answer Is there any way to enforce padding between subroutines using the scatter file? Latest yesterday by Ghantaz 8 replies 265 views
Suggested answer A low-overhead real time counter consistent cross processor cores Latest yesterday by Zhifei Yang 1 replies 8636 views