Cortex-A9

The Cortex-A9 processor is a performance and power optimized multi-core processor and it is one of Arm's most widely deployed and mature applications processors.

Information on Cortex-A9.

Getting Started

The Cortex-A9 processor features a dual-issue, partially out-of-order pipeline and a flexible system architecture with configurable caches and system coherency using the ACP port. The Cortex-A9 processor achieves a better than 50% performance over the Cortex-A8 processor in a single-core configuration.

Characteristics

The Cortex-A9 processor is a performance and power optimized multi-core processor. It features a dual-issue, partially out-of-order pipeline and a flexible system architecture with configurable caches and system coherency using ACP port. The Cortex-A9 processor achieves a better than 50% performance over the Cortex-A8 processor in a single-core configuration.


  • Manual containing technical information.
  • Cortex-A9 Technical Reference Manual

    For system designers and software engineers, the Cortex-A9 manual provides information on implementing and programming Cortex-A9 based devices.

    Read here
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv7-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Development Tools

Cortex-A comparison table (Armv7-A)
Feature Cortex-A5 Cortex-A7 Cortex-A9 Cortex-A15 Cortex-A17
Instruction set architecture and extensions Armv7-A Armv7-A
LPAE Virtualization
Armv7-A Armv7-A
LPAE Virtualization
Armv7-A
LPAE Virtualization
Pipeline In order In order Out of order Out of order Out of order
Superscalar No Partial Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Included
Floating Point Unit only Optional Optional Optional Optional Included
Cryptography Unit No No No No No
Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No
L1 I-Cache / D-Cache 4k-64KB 8k-64KB 16k-64KB 32KB/32KB 32k-64KB/32KB
L2 Cache External L2C-310 Up to 1MB External L2C-310 512KB-4MB 256KB-8MB
L3 Cache NA NA NA NA NA
ECC / Parity   No Yes Yes L2 only
LPAE No Yes No Yes Yes
Bus Interfaces AXI ACE AXI ACE or CHI ACE
ACP Optional No Optional Optional Optional
Peripheral Port     No No Yes
Functional Safety Support          
Security TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller Optional Integrated GIC v1 (MP only) Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GICv2 External GICv2
Generic Timer No Yes Yes Armv8-A Armv8-A

Cortex-A comparison (Armv8-A)

Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 Cortex-A65 Cortex-A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A76AE Cortex-A77 Cortex-A78
Instruction set architecture and extensions Armv8-A AArch32 only Armv8-A AArch64 only Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A
AArch64
only

Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only)
Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A
AArch64,
AArch32 at EL0

Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Armv8-A
AArch64,
AArch32 at EL0

Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Armv8-A
AArch64
AArch32 at EL0

Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline In order In order In order In order In order Out of order Out of order Out-of-order Out of order Out of order Out-of-order Out-of-order Out-of-order Out-of-order
Out-of-order
Superscalar       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Yes
Neon and Floating Point Unit Optional Optional Optional Optional Optional Included Included Included Included Included Included Included Included Included
Included
Floating Point Unit only N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included Included
Included
Cryptography Unit Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional
Optional
Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 44-bit 40-bit 44-bit 40-bit 40-bit 40-bit
40-bit
Dual Core Lock-Step (DCLS) No No No No No No No Yes (in safety-mode) No No No No Yes (in safety-mode) No
No
L1 I-Cache / D-Cache 8KB-64KB 8KB-64KB 8K-64KB 8KB-64KB 16KB-64KB 48KB/32KB 16KB to 64KB 16KB to 64KB 48KB/32KB-64KB 32KB/32KB-64KB 64KB 64KB 64KB 64KB
64KB
L2 Cache 128KB-1MB 128KB-1MB 128KB-1MB 128KB-2MB 64KB-256KB 512KB-2MB 64KB to 256KB 64KB to 256KB 512KB-4MB 256KB-8MB 256KB to 512KB 256KB to 512KB 256KB to 512KB 256KB to 512KB
256KB to 512KB
L3 Cache NA NA NA NA Optional
From 256KB to 4MB
NA Optional 512KB to 4MB Optional 512KB to 4MB NA NA Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB
Optional 512KB to 4MB
ECC / Parity Yes Yes Yes Yes Yes Yes Yes Yes Yes L2 only Yes Yes Yes Yes
Yes
LPAE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Yes
Bus Interfaces ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI ACE or CHI
ACE or CHI
ACP Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional Optional
Optional
Peripheral Port         Optional   Optional Optional     Optional Optional Optional Optional
Optional
Functional Safety Support Yes Yes Yes Yes Yes Yes   Yes Yes   Yes Yes Yes Yes
ASIL D systematic
Security TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone
TrustZone
Interrupt Controller External
GICv3
External
GICv3
External
GICv3
External
GICv3
External
GICv4
External
GICv3
External
GICv4
External
GICv4
External
GICv3
External
GICv3
External
GICv4
External
GICv4
External
GICv4
External
GICv4
External
GICv4
Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A
Armv8-A

 

Get Support

Related IP

The Cortex-A9 processor can be incorporated into an SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A9 processor is fully supported by Arm development tools. Related IP includes:

 

Graphic IP
Other IP
Tools

Mali GPUs

Mali Display Processors

Mali-V500 Video Processor

CoreLink Network Interconnect Family

CoreLink System Controllers

Interrupt Controllers

CoreSight SoC-400

POP IP

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models

 


Community Blogs

Community Forums

Not answered initialisation of DRAM ECC with Cortex A9 CPU 0 votes 17 views 0 replies Started 6 hours ago by flongnos Answer this
Suggested answer FVP MPS2 UART memory map 0 votes 287 views 2 replies Latest 10 hours ago by Gabor M. Answer this
Suggested answer Cortex A9 MMU 0 votes 1433 views 7 replies Latest 22 hours ago by flongnos Answer this
Suggested answer Does the processor frequency change when switching from secure to non secure domain?
  • Cortex-M23
  • TrustZone for Armv8-M
0 votes 226 views 2 replies Latest yesterday by Ghantaz Answer this
Suggested answer Is there any way to enforce padding between subroutines using the scatter file?
  • Cortex-M23
  • Arm Assembly Language (ASM)
0 votes 267 views 8 replies Latest yesterday by Ghantaz Answer this
Suggested answer A low-overhead real time counter consistent cross processor cores 0 votes 8638 views 1 replies Latest yesterday by Zhifei Yang Answer this
Not answered initialisation of DRAM ECC with Cortex A9 CPU Started 6 hours ago by flongnos 0 replies 17 views
Suggested answer FVP MPS2 UART memory map Latest 10 hours ago by Gabor M. 2 replies 287 views
Suggested answer Cortex A9 MMU Latest 22 hours ago by flongnos 7 replies 1433 views
Suggested answer Does the processor frequency change when switching from secure to non secure domain? Latest yesterday by Ghantaz 2 replies 226 views
Suggested answer Is there any way to enforce padding between subroutines using the scatter file? Latest yesterday by Ghantaz 8 replies 267 views
Suggested answer A low-overhead real time counter consistent cross processor cores Latest yesterday by Zhifei Yang 1 replies 8638 views