Specifications

A highly power efficient mid-range application CPU built on Arm DynamIQ technology.

The Arm Cortex-A55 processor is a market-leading CPU that delivers the best combination of power efficiency and performance in its class. It is part of the first generation of application CPUs based on DynamIQ technology and features the latest Armv8-A architecture extensions, with dedicated machine learning instructions. 

The Cortex-A55 incorporates an extensively redesigned microarchitecture system that improves performance across the board while being very competitive in area and power efficiency. It delivers up to 18% more performance at 15% better power efficiency when compared to its predecessor, the Cortex-A53. 

Designed to be an extremely scalable CPU, the versatile Cortex-A55 can be used to address a wide range of applications with diverging cost, from the edge to the cloud. The Cortex-A55 can be implemented in both stand-alone applications or as a ‘LITTLE’ CPU to the Cortex-A7x series with DynamIQ big.LITTLE.

Information on Cortex-A55.

Arm Cortex-A55 CPU

General Architecture Armv8-A (Harvard)
  Extensions Armv8.1 extensions,
Armv8.2 extensions,
Cryptography extensions,
RAS extensions,
Armv8.3 (LDAPR instructions only)
  ISA Support A64, A32, and T32 instruction sets 
Microarchitecture Pipeline In-order
  Superscalar Yes
  Neon / Floating Point Unit  Optional
  Cryptography Unit
Optional
  Max Number of CPUs in Cluster Eight (8)
  Physical Addressing (PA) 40-bit
Memory System and External Interfaces L1 I-Cache / D-Cache 16KB to 64KB
  L2 Cache Optional, 64KB to 256KB
  L3 Cache Optional, 512KB to 4MB
  ECC Support Yes 
  LPAE Yes 
  Bus Interfaces ACE or CHI 
  ACP Optional 
  Peripheral Port Optional 
Other Functional Safety Support ASIL D systematic
  Security TrustZone 
  Interrupts GIC Interface, GICv4 
  Generic Timer  Armv8-A
  PMU PMUv3 
  Debug Armv8-A (plus Armv8.2-A extensions) 
  CoreSight CoreSightv3 
  Embedded Trace Macrocell ETMv4.2 (instruction trace)

Characteristics

Superior efficiency
Featuring an extensive microarchitecture redesign, the Cortex-A55 processor is able to achieve breakthrough performance, while maintaining similar levels of power and 15% better power efficiency than the Cortex-A53. The efficiency gain enables the Cortex-A55 to deliver higher sustained performance for thermally constrained applications as well as exceptional power savings for low-power applications. 

Memory subsystem
The Cortex-A55 features an integrated, configurable L2 cache within each CPU that achieves more than 50% reduced latency for memory accesses. It contains an L3 cache that is shared across up to eight Cortex-A55 CPUs within a single cluster. This new memory subsystem, which is designed for high bandwidth, improves overall compute performance while also reducing system power.

State-of-the-art architecture
With support for the Armv8-A architecture, the Cortex-A55 processor is backwards-compatible with existing software and comes with a wealth of existing ecosystem support, from tools to Operating Systems. It also features the latest architecture extensions that introduce new NEON instructions for machine learning, advanced safety features and more support for Reliability, Accessibility and Serviceability (RAS).

DynamIQ big.LITTLE
The Cortex-A55 processor is designed to be compatible with the Cortex-A75 CPU for DynamIQ big.LITTLE, the next generation in big.LITTLE technology. DynamIQ big.LITTLE offers support for new CPU configurations, such as 1xbig + 7xLITTLE and 1xbig + 3xLITTLE, that achieve superior area efficiency, while delivering exceedingly high performance for richer, immersive experiences on all touchscreen-based devices.


Cortex-A comparison table for Armv7-A and Armv8-A

Download the following PDF datasheet to compare the specifications of Cortex-A Armv7-A and Armv8-A processors.

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Cortex-A comparison (Armv8-A)

Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 Cortex-A65 Cortex-A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A76AE Cortex-A77 Cortex-A78
Instruction set architecture and extensions Armv8-A AArch32 only Armv8-A AArch64 only Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A
AArch64
only

Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only)
Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A
AArch64,
AArch32 at EL0

Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Armv8-A
AArch64,
AArch32 at EL0

Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Armv8-A
AArch64
AArch32 at EL0

Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline In order In order In order In order In order Out of order Out of order Out-of-order Out of order Out of order Out-of-order Out-of-order Out-of-order Out-of-order
Out-of-order
Superscalar       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Yes
Neon and Floating Point Unit Optional Optional Optional Optional Optional Included Included Included Included Included Included Included Included Included
Included
Floating Point Unit only N/A N/A N/A N/A N/A Included Included Included Included Included Included Included Included Included
Included
Cryptography Unit Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional Optional
Optional
Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 44-bit 40-bit 44-bit 40-bit 40-bit 40-bit
40-bit
Dual Core Lock-Step (DCLS) No No No No No No No Yes (in safety-mode) No No No No Yes (in safety-mode) No
No
L1 I-Cache / D-Cache 8KB-64KB 8KB-64KB 8K-64KB 8KB-64KB 16KB-64KB 48KB/32KB 16KB to 64KB 16KB to 64KB 48KB/32KB-64KB 32KB/32KB-64KB 64KB 64KB 64KB 64KB
64KB
L2 Cache 128KB-1MB 128KB-1MB 128KB-1MB 128KB-2MB 64KB-256KB 512KB-2MB 64KB to 256KB 64KB to 256KB 512KB-4MB 256KB-8MB 256KB to 512KB 256KB to 512KB 256KB to 512KB 256KB to 512KB
256KB to 512KB
L3 Cache NA NA NA NA Optional
From 256KB to 4MB
NA Optional 512KB to 4MB Optional 512KB to 4MB NA NA Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB
Optional 512KB to 4MB
ECC / Parity Yes Yes Yes Yes Yes Yes Yes Yes Yes L2 only Yes Yes Yes Yes
Yes
LPAE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Yes
Bus Interfaces ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI ACE or CHI
ACE or CHI
ACP Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional Optional
Optional
Peripheral Port         Optional   Optional Optional     Optional Optional Optional Optional
Optional
Functional Safety Support Yes Yes Yes Yes Yes Yes   Yes Yes   Yes Yes Yes Yes
ASIL D systematic
Security TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone
TrustZone
Interrupt Controller External
GICv3
External
GICv3
External
GICv3
External
GICv3
External
GICv4
External
GICv3
External
GICv4
External
GICv4
External
GICv3
External
GICv3
External
GICv4
External
GICv4
External
GICv4
External
GICv4
External
GICv4
Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A
Armv8-A