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SHADD (vector)

Signed Halving Add.


SHADD Vd.T, Vn.T, Vm.T


Is the name of the SIMD and FP destination register.
Is an arrangement specifier, and can be one of 8B, 16B, 4H, 8H, 2S or 4S.
Is the name of the first SIMD and FP source register.
Is the name of the second SIMD and FP source register.


Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD and FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD and FP register.

The results are truncated. For rounded results, see SRHADD (vector).

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.