FCVTN, FCVTN2 (vector)
Floating-point Convert to lower precision Narrow (vector).
- Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements. See <Q> in the Usage table.
- Is the name of the SIMD and FP destination register.
- Is an arrangement specifier, and can be one of the values shown in Usage.
- Is the name of the SIMD and FP source register.
Is an arrangement specifier, and can be either
Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD and FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD and FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the FPCR.
FCVTN instruction writes the vector to the lower half of the destination register and clears the upper half, while the
FCVTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.
The following table shows the valid specifier combinations:
Table 20-8 FCVTN, FCVTN2 (Vector) specifier combinations