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CLS (vector)

Count Leading Sign bits (vector).


CLS Vd.T, Vn.T


Is the name of the SIMD and FP destination register.
Is an arrangement specifier, and can be one of 8B, 16B, 4H, 8H, 2S or 4S.
Is the name of the SIMD and FP source register.


Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD and FP register, places the result into a vector, and writes the vector to the destination SIMD and FP register. The count does not include the most significant bit itself.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.