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FMUL (scalar, by element)

Floating-point Multiply (by element).


FMUL Vd, Vn, Vm.Ts[index]


Is a width specifier, and can be H, S, or D.
Is the number of the SIMD and FP destination register.
Is the number of the first SIMD and FP source register.
Is an element size specifier, and can be H, S, or D.
Is the element index, H.
Is the name of the second SIMD and FP source register in the range 0 to 31.

Architectures supported (scalar)

Supported in the Arm®v8.2 architecture and later.


Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD and FP register by the specified value in the second source SIMD and FP register, places the results in a vector, and writes the vector to the destination SIMD and FP register. All the values in this instruction are floating-point values.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

The following table shows the valid specifier combinations:

Table 19-8 FMUL (Scalar, single-precision and double-precision) specifier combinations

V Ts index
S S 0 to 3
D D 0 or 1