Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector).
Hn ; Scalar half precision
n ; Scalar single-precision and double-precision
- Is the 16-bit name of the SIMD and FP destination register.
- Is the 16-bit name of the SIMD and FP source register.
Is a width specifier, and can be either
- Is the number of the SIMD and FP destination register.
- Is the number of the SIMD and FP source register.
Architectures supported (scalar)
Supported in the Arm®v8.2 architecture and later.
Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD and FP destination register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.