Store Register Halfword (immediate).
simm ; Post-index general registers
simm]! ; Pre-index general registers
pimm}] ; Unsigned offset general registers
- Is the signed immediate byte offset, in the range -256 to 255.
- Is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0.
- Is the 32-bit name of the general-purpose register to be transferred.
- Is the 64-bit name of the general-purpose base register or stack pointer.
Store Register Halfword (immediate) stores the least significant halfword of a 32-bit register to memory. The address that is used for the store is calculated from a base register and an immediate offset. For information about memory accesses, see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.