Load Register Signed Halfword (immediate).
simm ; 32-bit, Post-index
simm ; 64-bit, Post-index
simm]! ; 32-bit, Pre-index
simm]! ; 64-bit, Pre-index
pimm}] ; 32-bit
pimm}] ; 64-bit
- Is the 32-bit name of the general-purpose register to be transferred.
- Is the signed immediate byte offset, in the range -256 to 255.
- Is the 64-bit name of the general-purpose register to be transferred.
- Is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0.
- Is the 64-bit name of the general-purpose base register or stack pointer.
Load Register Signed Halfword (immediate) loads a halfword from memory, sign-extends it to 32 bits or 64 bits, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset. For information about memory accesses, see Load/Store addressing modes in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.