Signed Rounding Shift Right and Accumulate (immediate).
- Is the name of the SIMD and FP destination register.
- Is an arrangement specifier, and can be one of the values shown in Usage.
- Is the name of the SIMD and FP source register.
- Is the right shift amount, in the range 1 to the element width in bits, and can be one of the values shown in Usage.
Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD and FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD and FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA (vector).
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
The following table shows the valid specifier combinations:
Table 20-77 SRSRA (Vector) specifier combinations
|8B||1 to 8|
|16B||1 to 8|
|4H||1 to 16|
|8H||1 to 16|
|2S||1 to 32|
|4S||1 to 32|
|2D||1 to 64|