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FMAXNMP (vector)

Floating-point Maximum Number Pairwise (vector).


FMAXNMP Vd.T, Vn.T, Vm.T ; Half-precision

FMAXNMP Vd.T, Vn.T, Vm.T ; Single-precision and double-precision



Is an arrangement specifier:

Can be one of 4H or 8H.
Single-precision and double-precision
Can be one of 2S, 4S or 2D.
Is the name of the SIMD and FP destination register.
Is the name of the first SIMD and FP source register.
Is the name of the second SIMD and FP source register.

Architectures supported (vector)

Supported in the Arm®v8.2 architecture and later.


Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD and FP register after the vector elements of the second source SIMD and FP register, reads each pair of adjacent vector elements in the two source SIMD and FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD and FP register. All the values in this instruction are floating-point values.

NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result is the numerical value, otherwise the result is identical to FMAX (scalar).

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps in the Arm® Architecture Reference Manual Arm®v8, for Arm®v8‑A architecture profile.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.