SMLAL, SMLAL2 (vector, by element)
Signed Multiply-Add Long (vector, by element).
- Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements. See <Q> in the Usage table.
- Is the name of the SIMD and FP destination register.
Is an arrangement specifier, and can be either
- Is the name of the first SIMD and FP source register.
- Is an arrangement specifier, and can be one of the values shown in Usage.
Is the name of the second SIMD and FP source register:
must be in the range V0 to V15.
must be in the range V0 to V31.
Is an element size specifier, and can be either
- Is the element index, in the range shown in Usage.
Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD and FP register by the specified vector element in the second source SIMD and FP register, and accumulates the results with the vector elements of the destination SIMD and FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.
SMLAL instruction extracts vector elements from the lower half of the first source register, while the
SMLAL2 instruction extracts vector elements from the upper half of the first source register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
The following table shows the valid specifier combinations:
Table 20-45 SMLAL, SMLAL2 (Vector) specifier combinations
|-||4S||4H||H||0 to 7|
|2||4S||8H||H||0 to 7|
|-||2D||2S||S||0 to 3|
|2||2D||4S||S||0 to 3|