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FNEG (vector)

Floating-point Negate (vector).


FNEG Vd.T, Vn.T ; Half-precision

FNEG Vd.T, Vn.T ; Single-precision and double-precision



For the half-precision variant: is an arrangement specifier:

Can be one of 4H or 8H.
Single-precision and double-precision
Can be one of 2S, 4S or 2D.
Is the name of the SIMD and FP destination register.
Is the name of the SIMD and FP source register.

Architectures supported (vector)

Supported in ARMv8.2 and later.


Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD and FP register, writes the result to a vector, and writes the vector to the destination SIMD and FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.