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SRSRA (scalar)

Signed Rounding Shift Right and Accumulate (immediate).


SRSRA Vd, Vn, #shift


Is a width specifier, D.
Is the number of the SIMD and FP destination register.
Is the number of the first SIMD and FP source register.
Is the right shift amount, in the range 1 to 64.


Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD and FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD and FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA in the ARMv8-A Architecture Reference Manual.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.