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# FCMP

Floating-point quiet Compare (scalar).

### Syntax

``` FCMP Hn, Hm ; Half-precision ```

``` FCMP Hn, #0.0 ; Half-precision, zero ```

``` FCMP Sn, Sm ; Single-precision ```

``` FCMP Sn, #0.0 ; Single-precision, zero ```

``` FCMP Dn, Dm ; Double-precision ```

``` FCMP Dn, #0.0 ; Double-precision, zero ```

Where:

`Hn`

Depends on the instruction variant:

Half-precision
For the half-precision variant: is the 16-bit name of the first SIMD and FP source register
Half-precision, zero
For the half-precision, zero variant: is the 16-bit name of the SIMD and FP source register
`Hm`
Is the 16-bit name of the second SIMD and FP source register.
`Sn`

Depends on the instruction variant:

Single-precision
Is the 32-bit name of the first SIMD and FP source register.
Single-precision, zero
Is the 32-bit name of the SIMD and FP source register.
`Sm`
Is the 32-bit name of the second SIMD and FP source register.
`Dn`

Depends on the instruction variant:

Double-precision
Is the 64-bit name of the first SIMD and FP source register.
Double-precision, zero
Is the 64-bit name of the SIMD and FP source register.
`Dm`
Is the 64-bit name of the second SIMD and FP source register.

## NaNs

The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==, > or unordered. If either or both of the operands are NaNs, they are unordered, and all three of (Operand1 < Operand2), (Operand1 == Operand2) and (Operand1 > Operand2) are false. This case results in the FPSCR flags being set to N=0, Z=0, C=1, and V=1.

## Usage

Floating-point quiet Compare (scalar). This instruction compares the two SIMD and FP source register values, or the first SIMD and FP source register value and zero. It writes the result to the PSTATE.{N, Z, C, V} flags.

It raises an Invalid Operation exception only if either operand is a signaling NaN.

A floating-point exception can be generated by this instruction. Depending on the settings in FPCR in the ARMv8-A Architecture Reference Manual, the exception results in either a flag being set in FPSR in the ARMv8-A Architecture Reference Manual, or a synchronous exception being generated. For more information, see Floating-point exception traps in the ARMv8-A Architecture Reference Manual.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.